Memory Controller Power Defect Management via Module Rerouting
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Solution Overview
Problem
Storage devices face challenges in managing power defects, particularly when erase or program operations fail due to defective power modules supplying voltages to multiple word line groups across different memory blocks, leading to data integrity issues and reduced reliability.
Innovation Solution
A memory controller with a fail block detector, fail block manager, and power defect controller is implemented to identify and reroute voltages from defective power modules to functional ones, ensuring that memory blocks with failed operations are reassigned to healthy power sources, thereby maintaining data integrity and system reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single power module supplies voltages to multiple word line groups across different memory blocks, then the device complexity is reduced, but the reliability deteriorates when the power module becomes defective
Solution Approach 1:
The patent segments the power supply function by dividing the memory device into multiple independent power modules, where each power module is responsible for supplying voltages to specific word line groups in specific memory blocks. This segmentation isolates defects to individual modules, preventing a single point of failure from affecting the entire system.
Solution Approach 2:
The patent implements local quality by assigning different power modules to different spatial regions (memory blocks and word line groups). When a power module is detected as defective, only the local region it serves is affected, while other regions continue to operate normally with their dedicated power modules.
2Reliability
If power modules are increased to provide redundant power supply, then the reliability is improved, but the device complexity increases
Solution Approach 1:
The patent implements a feedback mechanism where the memory controller continuously monitors the operational status of each power module and memory block. When a defect is detected in a power module or memory block, the controller receives feedback and automatically reroutes operations to healthy components, maintaining system reliability without requiring manual intervention.
Solution Approach 2:
The patent introduces dynamic reconfiguration capability that allows the system to adapt its power module assignments in real-time. When a power module fails, the system dynamically reroutes word line groups from the defective module to other functional power modules, and similarly reroutes memory blocks to different power modules, ensuring continuous operation.
3Device complexity
If defective power modules are not replaced, then the device complexity remains low, but data integrity issues occur
Solution Approach 1:
The patent performs preliminary detection and isolation of defective power modules before they can cause data integrity issues. By continuously monitoring power module status and proactively identifying defects, the system prevents faulty power supply from reaching memory operations, thereby protecting data integrity through preventive action.
Solution Approach 2:
The patent extracts or isolates the defective power module from the operational system through logical separation. When a power module is detected as defective, the system removes it from the active power supply network and reroutes its associated memory blocks and word line groups to healthy power modules, preventing the defective module from compromising data integrity.
Data Source
AI summary
A memory controller controls a memory device including a plurality of memory blocks and a plurality of power modules respectively providing voltages to a plurality of word line groups, the memory controller comprising: a fail block detector detecting fail blocks on which an erase operation has failed among the plurality of memory blocks, and detecting fail word line groups among a plurality of word line groups included in each of the fail blocks; a fail block manager detecting, among the plurality of power modules, a defective power module providing the voltages to two or more fail word line groups each included in a different fail block among the fail blocks; and a power defect controller controlling the memory device such that the defective power module is changed to another power module among the plurality of power modules.