Memory Controller Peak Power Management via Command Delay

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Memory systems face operating errors due to peak power exceeding limited power supplies when multiple memory devices operate simultaneously, leading to potential reliability issues.

Innovation Solution

A memory system with a controller that monitors power consumption and delays peak power operations of selected memory devices to prevent total peak power from exceeding the limit, using a flash interface layer to manage command execution and distribute peak power periods.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple memory devices operate simultaneously to improve productivity, then data processing speed increases, but peak power exceeds the limited power supply causing operating errors

Engineering Contradiction:
Improvedata processing speedVSAvoidoperating error rate
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The controller predicts peak power periods in advance by storing peak power period information and proactively delays operations before peak power exceeds the limit, preventing operating errors before they occur

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system dynamically adjusts the operation timing of memory devices based on real-time power consumption monitoring and predicted peak power periods, flexibly scheduling operations to avoid power overload while maintaining processing efficiency

Inventive Principle:
Principle #15Dynamics

2Reliability

If the controller delays peak power operations to prevent power overload, then reliability improves, but operation time is extended and productivity decreases

Engineering Contradiction:
Improveoperating error rateVSAvoidoperation delay time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The controller schedules memory operations in periodic cycles, grouping operations during low-power periods and deferring peak power operations to appropriate time slots, creating a rhythmic operation pattern that prevents overload while minimizing total delay

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The system continuously monitors actual power consumption and compares it with predicted peak power periods, using this feedback to dynamically adjust operation scheduling and reduce unnecessary delays while maintaining power safety

Inventive Principle:
Principle #23Feedback

3Power

If the controller monitors and manages peak power by delaying operations, then power consumption is controlled, but device complexity increases

Engineering Contradiction:
Improvepeak power levelVSAvoidcontroller complexity
Core Design Contradiction:
PowerVSDevice complexity

Solution Approach 1:

The memory system performs self-power management by automatically monitoring its own power consumption, predicting peak power periods, and scheduling operations to prevent overload, eliminating the need for external power management complexity

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The controller stores peak power period information in advance and proactively schedules operations to avoid peak power conflicts, performing power management decisions before operations occur rather than reacting in real-time, which simplifies the control logic

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11392302B2Memory system and operating method thereof
Publication Date: 2022.07.19 SK HYNIX INC
  • US11392302B2 patent drawing
  • US11392302B2 patent drawing
  • US11392302B2 patent drawing

AI summary

A memory system includes a plurality of memory devices storing data, a processor generating commands at a request of a host, and a flash interface layer transferring the commands to the plurality of memory devices based on power consumptions of the plurality of memory devices, and delaying execution or transfer of commands one or more of the plurality of memory devices when a total peak power of the plurality of memory devices is expected to exceed a limit level.