Memory Controller Power Mode Selection via Data Transfer State
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Solution Overview
Problem
Current solid state drives (SSDs) with NAND-type flash memory face challenges in optimizing power consumption, as they lack efficient mechanisms to dynamically adjust power states based on data transfer activity, leading to suboptimal energy usage.
Innovation Solution
A memory system with a controller circuit that implements multiple low power consumption modes, managed by a PCIe link controller, which selects the appropriate mode based on data transfer state through the NVMe standard, optimizing the PCIe physical layer's power state using ASPM and specific control signals to reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the SSD maintains the physical layer in a high-performance state continuously, then data transfer speed is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic power state adjustment by transitioning the PCIe physical layer between active and low-power states based on data transfer activity. The controller monitors data transfer status and dynamically switches the physical layer to low-power mode when idle, rather than maintaining a fixed high-performance state, thus resolving the contradiction between speed and power consumption.
Solution Approach 2:
The patent changes the operational parameters of the physical layer by selecting from multiple predefined low-power modes (e.g., L0, L1, L2) with different power consumption levels. This allows the system to adjust the balance between performance and energy efficiency based on actual data transfer needs, transforming the fixed parameter state into a variable one that optimizes both speed and power usage.
2Use of energy by moving object
If the SSD frequently transitions between power states, then power consumption is reduced, but system complexity increases
Solution Approach 1:
The patent segments the power state management into distinct, predefined low-power modes (L0, L1, L2) and an active state. Each mode represents a specific power consumption level with associated entry/exit conditions. This segmentation simplifies the control logic by providing discrete, manageable states rather than a continuous or ambiguous power management approach.
Solution Approach 2:
The controller continuously monitors the data transfer status of the physical layer and uses this feedback to determine when to transition between power states. The feedback mechanism triggers state changes based on predefined conditions (e.g., no data transfer for a specified period), creating an automated closed-loop system that reduces complexity by eliminating manual intervention and providing deterministic control.
3Use of energy by moving object
If the SSD uses multiple low power consumption modes, then energy efficiency is improved, but control complexity increases
Solution Approach 1:
The patent implements a universal power state management mechanism that handles multiple low-power modes through a single integrated control framework. The same controller logic manages transitions between L0, L1, L2 modes and the active state, using unified entry/exit conditions and standardized transition procedures. This multi-functional approach improves energy efficiency while avoiding the need for separate control mechanisms for each power mode.
Data Source
AI summary
A memory system includes a nonvolatile semiconductor memory, and a controller circuit that includes a physical layer and is configured to store information defining a plurality of low power consumption modes for setting the physical layer to a low power consumption state while controlling the physical layer according to a first standard, and control input and output of signals between the physical layer and the nonvolatile semiconductor memory according to a second standard. The controller circuit selects one of the low power consumption modes based on a data transfer state of the physical layer.