Memory Controller Power-Off Map Data Flush

Solution Overview

Problem

Current memory systems face challenges in rapidly flushing large amounts of data protected by ECC encoding from volatile memory to nonvolatile memory, which delays power-off times due to bottlenecks caused by low throughput in error correction components.

Innovation Solution

Incorporating a high-throughput error correction component that bypasses the low-throughput VM ECC component during power-off, allowing direct memory access to rapidly transfer error-corrected map data to the nonvolatile memory, and selectively removing or maintaining parity bits to optimize data transfer modes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If data is flushed through the VM ECC component during power-off, then data reliability is maintained through error correction, but the power-off time is extended due to low throughput

Engineering Contradiction:

Improvedata reliabilityVSAvoidpower-off time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent introduces a second ECC component as an intermediary pathway that specifically handles power-off flushing operations. This separate ECC component acts as a mediator between the volatile memory and nonvolatile memory, providing a dedicated error correction path that operates in parallel to the main VM ECC component, thereby resolving the conflict between reliability and speed during power-off events.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent segments the error correction functionality into two distinct components: the VM ECC component for normal operations and a second ECC component for power-off flushing operations. This segmentation allows each component to be optimized for its specific purpose, with the second ECC component dedicated solely to handling power-off scenarios with higher throughput capability.

Inventive Principle:

Principle #1Segmentation

2Loss of time

If a high-throughput ECC component is added to bypass the VM ECC component, then power-off time is reduced through rapid data transfer, but the device complexity increases

Engineering Contradiction:

Improvepower-off timeVSAvoiddevice complexity

Core Design Contradiction:

Loss of timeVSDevice complexity

Solution Approach 1:

The patent segments the error correction functionality into two distinct components: the VM ECC component for normal operations and a second ECC component for power-off flushing operations. This segmentation allows each component to be optimized for its specific purpose, with the second ECC component dedicated solely to handling power-off scenarios with higher throughput capability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic routing logic that automatically selects the appropriate ECC component based on the operational context. During normal operations, data flows through the VM ECC component, while during power-off events, the system dynamically switches to use the second ECC component for rapid flushing, thereby adapting the system's behavior to match the operational requirements.

Inventive Principle:

Principle #15Dynamics

3Productivity

If map data is rapidly transferred to nonvolatile memory during power-off, then power-off time is shortened, but data transfer bottlenecks occur without sufficient error correction capacity

Engineering Contradiction:

Improvedata transfer speedVSAvoiderror correction capability

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent segments the error correction functionality into two distinct components: the VM ECC component for normal operations and a second ECC component for power-off flushing operations. This segmentation allows each component to be optimized for its specific purpose, with the second ECC component dedicated solely to handling power-off scenarios with higher throughput capability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a second ECC component as an intermediary pathway that specifically handles power-off flushing operations. This separate ECC component acts as a mediator between the volatile memory and nonvolatile memory, providing a dedicated error correction path that operates in parallel to the main VM ECC component, thereby resolving the conflict between reliability and speed during power-off events.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS11422889B2Memory system and controller for storing map data of volatile memory into nonvolatile memory device during power off operation

Publication Date: 2022.08.23 SK HYNIX INC

AI summary

A memory system includes: a nonvolatile memory device; a processor configured to generate a first map chunk including mapping information for accessing the nonvolatile memory device; a first error correction code (ECC) component configured to generate a first map codeword by adding a first parity bit to the first map chunk; a volatile memory configured to store the first map codeword; a second ECC component configured to generate first map data by performing decoding on the first map codeword that is outputted from the volatile memory and bypasses the first ECC component when the memory system is powered off; and a direct memory access (DMA) component configured to provide the first map data to the nonvolatile memory device.