Memory Controller Power-Saving State Management
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Solution Overview
Problem
Existing memory control methods that reduce power consumption often require changing the function of the bus master, which can be impractical and error-prone, especially in integrated processors with multiple IP cores operating as bus masters.
Innovation Solution
A control device and method that shifts the memory controller into an execution standby state, allowing it to accept access requests while temporarily creating a busy state, enabling power-saving mode without altering the bus master's function, by using a memory controller management unit to manage the memory interface and physical layer parameters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a signal is sent to the bus master to stop access requests to the memory, then power consumption is reduced, but the function of the bus master is changed
Solution Approach 1:
Instead of controlling the bus master to stop access requests, the patent inverts the control direction by having the memory controller send a stop instruction signal to the bus master. This allows the memory controller to manage access requests without altering the bus master's fundamental function, resolving the contradiction between power reduction and operational simplicity.
Solution Approach 2:
The patent introduces a memory controller as an intermediary between the bus master and the memory. The memory controller manages access requests from multiple bus masters and controls memory access timing, enabling power-saving modes without requiring changes to bus master functions. The intermediary handles the complexity of coordinating multiple bus masters and managing memory power states.
2Loss of energy
If access requests to the memory are stopped by sending signals to bus masters, then power consumption is reduced, but system complexity increases
Solution Approach 1:
The memory controller is designed with multi-functionality to handle various bus masters (PCIe, USB, SATA, etc.) uniformly. It provides a universal interface for managing access requests from different types of bus masters, reducing the need for separate control mechanisms for each bus master type and thereby reducing overall system complexity while enabling power-saving features.
3Adaptability or versatility
If the memory controller manages multiple bus masters, then adaptability is improved, but control complexity increases
Solution Approach 1:
The memory controller is segmented into distinct functional units: a first data interface for accepting access requests from multiple bus masters, a first control interface for managing the data interface state, and a memory interface unit for executing access to the memory. This segmentation allows each unit to have a specific, simplified function while collectively providing adaptable support for various bus masters, reducing overall control complexity.
Data Source
AI summary
A processor controlling access to a memory includes: a physical layer controller executing data access to the memory; a memory controller accepting an access request to the memory from a plurality of bus masters and causing the physical layer controller to execute the access request; and a CPU. The CPU shifts the memory controller into a busy state to accept the access request and stand by for execution, when a condition to turn the memory into a power-saving state is satisfied. The CPU executes control to turn the memory into the power-saving state, with the memory controller being in the busy state.