Memory Controller Power-Off Recovery Checkpoint Mechanism

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing memory systems face challenges in quickly and stably processing data before and after power-off events, particularly in completing operations across multiple memory blocks, leading to inefficiencies and potential data loss.

Innovation Solution

A memory system with a controller that records checkpoint information for ongoing operations, performs dummy write operations on incomplete blocks after power-off, and recovers data by writing dummy data into adjacent pages, allowing for selective recovery of operations across memory blocks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If dummy write operations are performed on all memory blocks after power-off, then data recovery reliability is improved, but memory block utilization efficiency deteriorates

Engineering Contradiction:
Improvedata recovery reliabilityVSAvoidmemory block utilization efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent segments the set of memory blocks into two distinct groups: first memory blocks that completed their operations before power-off and second memory blocks that were undergoing operations when power-off occurred. This segmentation allows the system to apply different recovery strategies to different blocks, performing dummy write operations only on the second group while skipping the first group, thereby improving memory block utilization efficiency without compromising data recovery reliability for blocks that need it.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Instead of performing dummy write operations on all memory blocks (excessive action), the patent applies dummy write operations only to the subset of memory blocks that actually require recovery (partial action). By using checkpoint information to identify which blocks were incomplete at power-off, the system performs the minimal necessary recovery actions, avoiding unnecessary operations on blocks that already completed their tasks, thus improving efficiency while maintaining reliability.

Inventive Principle:
Principle #16Partial or excessive action

2Measurement precision

If checkpoint information is recorded for all operations, then data recovery accuracy is improved, but device complexity increases

Engineering Contradiction:
Improvedata recovery accuracyVSAvoiddevice complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent implements preliminary action by recording checkpoint information for ongoing operations before power-off can occur. The controller proactively tracks the status of each memory block operation and stores checkpoint data indicating which operations were in progress. This preliminary recording enables accurate recovery after power-off without requiring complex real-time analysis, as the system already has pre-prepared information about which blocks need recovery attention.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent extracts only the essential checkpoint information needed for recovery from the complete operation state. Rather than storing comprehensive operation logs or detailed status information for all memory blocks, the system extracts and stores only the critical checkpoint data indicating operation completion status. This selective extraction maintains high recovery accuracy while minimizing the complexity overhead of the checkpoint mechanism.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS10073651B2Memory system with power-off detection and recovery mechanism
Publication Date: 2018.09.11 MIMIRIP LLC
  • US10073651B2 patent drawing
  • US10073651B2 patent drawing
  • US10073651B2 patent drawing

AI summary

A memory system may include: a memory device including a plurality of memory blocks each memory block having a plurality of pages; and a controller suitable for performing a plurality of operations to first memory blocks among the memory blocks at a first time, recording a checkpoint information for the operations in the memory blocks, selecting second memory blocks among the first memory blocks through the checkpoint information at a second time after a power-off in the memory system while performing the operations, and performing a dummy write operation to the second memory blocks.