Memory Controller Parallel PRD Fetching
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Solution Overview
Problem
Current memory controllers face performance bottlenecks due to increased host operating speeds and bandwidth demands, particularly in handling commands and data communications with nonvolatile memory devices, as they often require synchronization and additional processing steps that delay data transfer operations.
Innovation Solution
A memory controller architecture with a first interface for host communication and a second interface for memory communication, featuring an emulation engine that generates DMA setup Frame Information Structures independently and a storage engine that fetches physical region descriptors before receiving DMA setup FIS, utilizing Advanced Host Control Interface (AHCI) and FIFO memory to optimize data transfer operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory controller waits for DMA setup FIS reception before fetching PRD, then data communication synchronization is maintained, but processing time increases and performance decreases
Solution Approach 1:
The storage engine fetches the Physical Region Descriptor (PRD) from the host in advance, before the DMA setup FIS is received from the emulation engine. This preliminary action allows the PRD to be ready when needed for data transfer operations, eliminating the waiting time that would otherwise occur.
Solution Approach 2:
The memory controller is divided into functionally independent engines: an emulation engine that generates DMA setup FIS, a storage engine that fetches PRD, and a data communication interface. This segmentation allows these operations to proceed in parallel rather than sequentially, resolving the contradiction between synchronization and processing time.
2Device complexity
If the memory controller uses sequential processing for command handling and data transfer setup, then processing simplicity is maintained, but overall performance and throughput are limited
Solution Approach 1:
The memory controller is segmented into distinct functional engines: an emulation engine for generating DMA setup FIS, a storage engine for fetching PRD, and a data communication interface. Each engine operates independently with its own processing pipeline, allowing parallel execution of multiple operations without increasing overall system complexity.
Solution Approach 2:
The storage engine continuously fetches PRD information while the emulation engine simultaneously generates DMA setup FIS. This continuous parallel operation ensures that no processing stage remains idle, maximizing throughput while maintaining manageable complexity through modular design.
Data Source
AI summary
A memory controller is provided. The memory controller may comprise a first interface configured to provide an interface for communications with a host, and a second interface configured to communicate with the host through the first interface and to provide an interface for communications with a memory. The second interface may include an emulation engine configured to generate a Direct Memory Access (DMA) setup Frame Information Structure (FIS) including ready state information for data communications with the host in response to a command transferred from the host. The second interface may include a storage engine configured to access the host to fetch a physical region descriptor (PRD) before the DMA setup FIS is received from the emulation engine.