Memory Controller Pre-Charging for Sensing Accuracy
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Solution Overview
Problem
High-density memory devices face challenges in accurate sensing operations due to parasitic capacitance in metal bit lines, leading to inadequate sensing current and reduced sensing accuracy, especially in high-density NAND flash memory devices.
Innovation Solution
The memory controller pre-charges the metal bit line parasitic capacitance using a pre-charging current, reducing channel current and distributing more sensing current as cell current, thereby minimizing voltage differences at the sense amplifier's output node, improving sensing accuracy by ensuring most sensing current is used for cell current during data reading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If sensing current is provided to high-density memory device, then data sensing is enabled, but parasitic capacitance causes voltage difference leading to inadequate sensing current and reduced sensing accuracy
Solution Approach 1:
The patent applies preliminary action by pre-charging the metal bit line parasitic capacitance before the sensing operation. The memory controller pre-charges the parasitic capacitance using a pre-charging current during a pre-charging stage, so that when sensing current is applied, the voltage difference caused by parasitic capacitance is minimized, ensuring adequate sensing current for accurate data reading
2Measurement precision
If pre-charging current is applied to metal bit line parasitic capacitance, then channel current is reduced and sensing accuracy is improved, but additional pre-charging stage is required
Solution Approach 1:
The patent applies segmentation by dividing the memory access cycle into distinct stages: a pre-charging stage for charging parasitic capacitance and a sensing stage for data reading. This segmentation allows the pre-charging current and sensing current to be independently controlled, reducing channel current during sensing while maintaining accurate data reading
3Quantity of substance
If sensing current is distributed to channel current due to voltage difference, then parasitic capacitance is charged, but inadequate cell current results for accurate sensing
Solution Approach 1:
The patent applies preliminary action by pre-charging the parasitic capacitance before sensing operations. This preliminary charging action ensures that when sensing current is applied, most of the current flows as cell current through the memory cells rather than being diverted as channel current to charge parasitic capacitance, thereby maintaining adequate sensing accuracy
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances sensing accuracy and efficiency by reducing noise and channel charging current, particularly beneficial for dense memory devices like TLC and QLC, and lowers reference sensing current, enabling faster and more accurate data access.
Implementation Method 1
where a memory cell array of the memory device has parasitic capacitance, e.g., corresponding to a metal bit line (MBL)
Data Source
AI summary
A memory device comprises a memory cell array with memory cells arranged in a cell string coupled to a metal bit line, a sense amplifier for providing a sensing current to the memory cell array, and a memory controller for controlling the sense amplifier to provide the sensing current to access data during a memory access cycle. The memory controller performs operations comprising: during a pre-charging stage of the memory access cycle, providing a pre-charging voltage to the sense amplifier to drive the sense amplifier such that a particular voltage is provided to the memory cell array; during a first sensing stage, providing the pre-charging voltage to the sense amplifier; and during a second sensing stage, providing a sensing voltage to drive the sense amplifier such that the particular voltage provided to the memory cell array is maintained.