Memory Controller Pre-Completion Response for Read Latency

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Solution Overview

Problem

Existing memory controllers face challenges in achieving improved operation speed and efficient data management, particularly in handling write requests and maintaining data integrity across cache lines.

Innovation Solution

The proposed memory controller incorporates a processor for generating commands, a scheduling circuit for managing command output, and a filtering circuit for providing pre-completion responses and handling write commands, thereby enhancing operation speed and data management efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the memory controller waits for write request completion before processing read requests, then data integrity is ensured, but read latency increases and operation speed decreases

Engineering Contradiction:

Improvedata integrityVSAvoidoperation speed

Core Design Contradiction:

ReliabilityVSSpeed

Solution Approach 1:

The filtering circuit provides a pre-completion response to the scheduling circuit before the actual write operation completes. This preliminary action allows the scheduling circuit to forward subsequent read requests to the main memory in advance, without waiting for the write completion signal from the memory device, thus reducing read latency while maintaining data integrity through the pre-completion mechanism

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The filtering circuit acts as an intermediary between the scheduling circuit and the main memory for write commands. It intercepts write commands, provides pre-completion responses to the scheduling circuit, and separately manages the actual write operation to the main memory. This intermediary mechanism decouples the read request processing from the write completion dependency, improving operation speed while ensuring data integrity

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If the memory controller processes commands sequentially, then command execution accuracy is maintained, but productivity decreases

Engineering Contradiction:

Improvecommand execution accuracyVSAvoidoperation throughput

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The memory controller is segmented into distinct functional circuits: a processor for generating commands, a scheduling circuit for managing command output, and a filtering circuit for handling write commands. This segmentation allows different parts of the system to operate independently and in parallel, with the scheduling circuit able to forward read requests while the filtering circuit manages write operations, thereby improving productivity without compromising command execution accuracy

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The scheduling circuit continuously forwards commands to the main memory without interruption or waiting for completion signals. Read requests are forwarded immediately without waiting for write completion, maintaining continuous useful action and improving operation throughput while the filtering circuit ensures write integrity through its pre-completion response mechanism

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS20250165392A1Memory controller for scheduling commands based on response for receiving write command, storage device including the memory controller, and operating method of the memory controller and the storage device

Publication Date: 2025.05.22 SK HYNIX INC

AI summary

An electronic device includes a memory controller having an improved operation speed. The memory controller includes a processor configured to generate commands for accessing data stored in a main memory, a scheduling circuit configured to store the commands and output the commands according to a preset criterion, and a filtering circuit configured to store information on an address of the main memory corresponding to a write command among the commands, provide a pre-completion response for the write command to the scheduling circuit upon receiving the write command, and provide the write command to the main memory.