Memory Controller Pre-Erase Mechanism for Wear Leveling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory card interfaces inefficiently handle wear leveling and pre-erase functions, leading to premature wear and inability to reuse memory blocks effectively, as they operate on large block granularity rather than file system allocation units.
Innovation Solution
A memory controller and method that allow for marking and erasing sectors or blocks at logical addresses, enabling memory wear leveling and garbage collection, even without immediate host device commands, using commands like DELETE_MULTIPLE_BLOCK or existing erase commands to manage memory maintenance and optimize write performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If erase operations are performed on large blocks rather than allocation units, then the memory card can handle erase operations efficiently, but the memory card cannot efficiently handle wear leveling and pre-erase functions at the file system level
Solution Approach 1:
The patent segments the erase operation into two distinct phases: a marking phase where allocation units are marked as deleted at the file system level, and a subsequent erase phase where physical blocks are erased. This segmentation allows the system to track individual allocation units for wear leveling while maintaining efficient block-level erase operations.
Solution Approach 2:
The patent implements preliminary marking of allocation units as deleted before actual physical erasure occurs. This preliminary action allows the file system to track which logical units need erasure and enables wear leveling algorithms to identify and relocate data from soon-to-be-erased blocks, optimizing both performance and longevity.
2Speed
If data is overwritten directly without pre-erase marking, then write operations are simple and fast, but the memory card appears full and cannot reuse deleted space efficiently
Solution Approach 1:
The patent implements preliminary marking of allocation units as deleted when files are removed, without immediately erasing the physical blocks. This allows the memory card to quickly acknowledge file deletion to the host while maintaining a list of marked units for subsequent erasure, enabling fast write operations and efficient memory reuse.
Solution Approach 2:
The patent introduces an intermediary data structure (marked allocation unit table) that tracks which logical units are deleted but not yet physically erased. This intermediary layer decouples the logical file system view from the physical storage state, allowing the system to manage deleted space efficiently without impacting write performance.
3Loss of time
If the memory card internally tracks full status without pre-erase, then the card can quickly report capacity, but it cannot perform wear leveling or reclaim space from deleted files
Solution Approach 1:
The patent segments the capacity tracking into immediate logical tracking (for quick capacity reporting) and deferred physical tracking (for wear leveling). The system maintains both a logical view of available space and a physical view of erased blocks, allowing simultaneous optimization of response time and reliability.
Data Source
Figure 1
Figure 2
AI summary
The specification and drawings present a new method, apparatus and software product for performance enhancement of a memory device (e.g., a memory card) using a pre-erase mechanism. The memory device can be, e.g., a memory card, a multimedia card or a secure digital card, etc. A new command or commands can be used to inform a memory device controller when the data in one particular sector, allocation unit or block can be deleted. Using that information the memory device controller then can be able to do some internal maintenance, e.g., by moving valid data from a fragmented erase block to another so that the fragmented erase block can be cleared and erased for future use as well as performing effective wear leveling maintenance and write performance optimization.