Memory Controller Pre-Resume Command for Parallel Read and Program Operations

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Solution Overview

Problem

Conventional memory systems face challenges in maintaining balanced quality across read, program, and erase operations, often degrading program or erase quality when improving read quality, and are unable to process different operations simultaneously efficiently.

Innovation Solution

A memory system and method that utilize a memory device with a page buffer circuit and a memory controller to suspend and resume operations, issuing a pre-resume command to resume suspended operations in parallel with data output, ensuring that operations are performed in a way that maintains read quality while preventing degradation of program or erase quality.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the memory system prioritizes improving read quality by suspending program or erase operations, then read quality is improved, but program quality or erase quality deteriorates

Engineering Contradiction:
Improveread qualityVSAvoidprogram quality or erase quality
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The memory controller issues a pre-resume command before the read operation completes, proactively preparing to resume the suspended program or erase operation. This preliminary action ensures that the suspended operation can be restarted with minimal delay, preventing quality degradation while still allowing the read operation to proceed.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system dynamically adjusts the timing of resuming suspended operations based on the read operation status. By monitoring whether the read operation has completed and using this information to determine when to issue the pre-resume command, the system flexibly manages the balance between read quality and program/erase quality.

Inventive Principle:
Principle #15Dynamics

2Reliability

If the memory system processes read operations separately from program and erase operations, then operation quality is maintained, but processing speed decreases

Engineering Contradiction:
Improveoperation qualityVSAvoidprocessing speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent merges the processing of read operations with suspended program or erase operations by allowing them to execute in parallel. The pre-resume command enables the suspended operation to restart while the read operation is still in progress, and both operations complete their execution simultaneously, effectively combining what were previously sequential operations into a parallel processing scheme.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

Instead of completely suspending program or erase operations during read operations, the system maintains continuity by quickly resuming them via the pre-resume command. This ensures that useful actions (program/erase operations) continue with minimal interruption while still accommodating read operations, thereby maintaining high processing speed without sacrificing operation quality.

Inventive Principle:
Principle #20Continuity of useful action

3Ease of operation

If the memory system waits for read operations to complete before resuming program or erase operations, then operation sequencing is simplified, but overall operation time increases

Engineering Contradiction:
Improveoperation sequencingVSAvoidoperation time
Core Design Contradiction:
Ease of operationVSLoss of time

Solution Approach 1:

The pre-resume command is issued in advance, before the read operation completes, rather than waiting for the read operation to finish. This preliminary resumption action reduces the idle time of suspended operations and allows parallel execution, thereby reducing overall operation time while maintaining manageable sequencing through the controller's timing logic.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11133068B2Memory device, memory controller, memory system and method for operating memory system
Publication Date: 2021.09.28 SK HYNIX INC
  • US11133068B2 patent drawing
  • US11133068B2 patent drawing
  • US11133068B2 patent drawing

AI summary

A memory system includes: a memory device including a memory cell array and a page buffer circuit, the memory device performing a data program operation or a data erase operation, suspending the data program operation or the data erase operation in response to a suspend command, performing a data read operation of storing read data from the memory cell array in the page buffer circuit in response to a read command, and performing a data output operation of outputting the read data stored in the page buffer circuit; and a memory controller outputting a pre-resume command to the memory device between a first time at which the data read operation is complete and a second time at which the data output operation starts.