Memory Controller Prefetch Throttling via Coherency Feedback
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Aggressive data prefetching can exacerbate memory access latencies by overwhelming memory controllers with a large number of data prefetch requests, leading to increased demand memory access times in data processing systems.
Innovation Solution
A memory controller system that receives data prefetch requests from multiple processor cores and responds with coherency messages to adjust the prefetch request rates, reducing the issuance of prefetch requests when an excess is detected, thereby managing the workload and mitigating latency issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If aggressive data prefetching is implemented to reduce memory access latencies, then data prefetching effectiveness is improved, but memory controller overload increases
Solution Approach 1:
The memory controller monitors the number of outstanding prefetch requests and provides feedback to processor cores by sending throttle/coherency responses when thresholds are exceeded. This feedback mechanism dynamically adjusts prefetch request rates to prevent memory controller overload while maintaining effective prefetching for applications that benefit from it.
Solution Approach 2:
The system dynamically adjusts the rate of prefetch request issuance based on real-time memory controller workload conditions. Processor cores reduce or resume prefetch request rates in response to coherency responses from the memory controller, allowing the prefetching behavior to adapt to changing system conditions and prevent sustained overload.
2Productivity
If the rate of data prefetch requests is increased to improve prefetching performance, then data prefetching effectiveness is improved, but demand memory access latency increases
Solution Approach 1:
The memory controller provides coherency responses that include throttle indicators to processor cores when prefetch request rates exceed acceptable thresholds. This feedback loop enables dynamic rate adjustment, allowing high prefetch throughput when memory capacity is available while preventing demand access latency degradation when the memory controller is overloaded.
Data Source
AI summary
According to a method of data processing, a memory controller receives a plurality of data prefetch requests from multiple processor cores in the data processing system, where the plurality of prefetch load requests include a data prefetch request issued by a particular processor core among the multiple processor cores. In response to receipt of the data prefetch request, the memory controller provides a coherency response indicating an excess number of data prefetch requests. In response to the coherency response, the particular processor core reduces a rate of issuance of data prefetch requests.