Memory Controller Priority Logic for Parallel Plane Read Operations
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Solution Overview
Problem
Current memory systems face inefficiencies in processing operations due to sequential execution of data output operations across multiple memory planes, leading to increased processing time and reduced capability during garbage collection, where planes with varying valid cluster ratios and operation times are not optimally prioritized.
Innovation Solution
A memory system with a controller that determines the priority of data output operations across multiple memory planes based on the total time required for both read and output operations, allowing for parallel execution and minimizing standby states by prioritizing planes with longer total operation times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If data output operations are executed sequentially across multiple memory planes, then the system is simpler to control, but the processing time increases and productivity decreases
Solution Approach 1:
The patent implements dynamic priority assignment for data output operations across multiple memory planes. The controller calculates total operation times (read + output) for each plane and assigns priorities dynamically, allowing the system to adapt to varying valid cluster ratios and operation characteristics. This dynamic approach enables parallel execution optimization without requiring complex static control structures.
Solution Approach 2:
The controller performs preliminary calculation of total operation times for each memory plane before executing data output operations. By calculating the sum of read operation time and output operation time in advance, the system can determine optimal execution priorities beforehand, reducing actual processing time and improving productivity without adding runtime complexity.
2Productivity
If data output operations are executed in parallel across multiple memory planes, then processing capability improves, but determining the optimal execution sequence becomes more complex
Solution Approach 1:
The patent changes the parameter used for priority determination from simple round-robin or fixed sequencing to total operation time (read time + output time). This parameter change provides a clear metric for prioritizing planes with longer valid cluster ratios, enabling efficient parallel execution. The approach balances complexity by using a straightforward time-based metric rather than complex multi-factor algorithms.
Solution Approach 2:
The system uses the inherent operation time characteristics of each memory plane to determine its own priority. Planes with longer total operation times naturally receive higher priority for data output operations, allowing the system to self-optimize without external intervention. This self-service mechanism reduces control complexity while maintaining high processing capability.
3Ease of operation
If planes with varying valid cluster ratios are processed without priority differentiation, then the control logic is simpler, but standby states increase and time is wasted
Solution Approach 1:
The patent introduces total operation time (read + output) as the key parameter for priority determination. This single parameter effectively captures the varying valid cluster ratios across planes and translates them into actionable priority levels. The approach maintains operational simplicity by using one clear metric while eliminating standby time through optimized sequencing.
Solution Approach 2:
The system uses feedback from the calculated total operation times to adjust the execution sequence of data output operations. By continuously monitoring and comparing operation times across planes, the controller can prioritize planes that would otherwise create standby states, reducing time loss while keeping control logic straightforward through time-based feedback.
Data Source
AI summary
According to one embodiment, a memory system includes nonvolatile memory including a plurality of memory areas and a memory controller. A read operation includes a first operation of reading data from a memory cell array and a second operation of transmitting at least a part of the read data to the memory controller. The memory controller determines, when executing the read operation in a first memory area and a second memory area in parallel, priorities of the second operation in the first memory area and the second operation in the second memory area based on a result of comparison between (A) a first total time period of the read operation in the first memory area and (B) a second total time of the read operation in the second memory area.