Memory Controller Dynamic Priority Background Read

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Solution Overview

Problem

Three-dimensional NAND-type flash memory systems face challenges in maintaining data retention over time, requiring efficient read operations to prevent memory cell data loss, which existing memory systems struggle to execute quickly and efficiently.

Innovation Solution

A memory system with a controller circuit that manages access histories and prioritizes a background read process to ensure data is read from all storage areas within a time limit, adjusting execution priorities to minimize latency for host access while completing the background read process without excessively delaying host access.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the background read process is executed with high priority to prevent data loss, then data retention is improved, but host access latency increases

Engineering Contradiction:
Improvedata retentionVSAvoidhost access latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system dynamically adjusts the execution priority of the background read process based on the operational state of the storage device. When the host access queue is not full, the background read process is executed at high priority to prevent data loss. When the queue is full or host access is intensive, the priority is reduced to minimize host access latency. This dynamic priority adjustment resolves the contradiction between data retention and host access latency.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the execution priority parameter of the background read process based on system conditions. The priority parameter is adjusted between high and low levels depending on whether the host access queue has available capacity, enabling the system to balance between preventing data loss and maintaining fast host access response.

Inventive Principle:
Principle #35Parameter changes

2Speed

If the background read process is delayed to reduce host access latency, then host access speed is improved, but data retention deteriorates

Engineering Contradiction:
Improvehost access speedVSAvoiddata retention
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The system employs dynamic priority adjustment where the background read process executes at high priority only when host access queue capacity allows. This prevents the background read from excessively delaying host access while still ensuring it completes within the time limit required for data retention, thus resolving the contradiction between host access speed and data retention.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system monitors the host access queue status and uses this feedback to adjust the execution priority of the background read process. When the queue is full, the background read priority is reduced; when space is available, priority is increased. This feedback mechanism ensures both host access speed and data retention requirements are met.

Inventive Principle:
Principle #23Feedback

3Reliability

If the background read process is executed quickly to prevent data loss, then data retention is improved, but host access is delayed

Engineering Contradiction:
Improvedata retentionVSAvoidhost access time
Core Design Contradiction:
ReliabilityVSDuration of action of moving object

Solution Approach 1:

The execution priority of the background read process is dynamically adjusted based on host access queue status. When the queue is not full, the background read executes quickly with high priority to prevent data loss. When the queue is full, the priority is reduced to avoid excessively delaying host access, thus balancing data retention with host access time.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the execution priority parameter of the background read process based on real-time system conditions. This parameter change enables the background read to execute quickly when safe to do so (improving data retention) while preventing excessive delays to host access by reducing priority when the queue is full.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10929061B2Memory system and memory control method
Publication Date: 2021.02.23 KIOXIA CORP
  • US10929061B2 patent drawing
  • US10929061B2 patent drawing
  • US10929061B2 patent drawing

AI summary

According to one embodiment, a memory system is configured to include a nonvolatile memory and a controller circuit. The controller circuit is electrically connected to the nonvolatile memory. The controller circuit executes a first process and a second process. The first process manages a history of accesses to first storage areas of the nonvolatile memory. The second process manages a progress of accesses to all storage areas of the first storage areas within a first time limit, based on the history of the accesses.