Memory Controller Dynamic Priority Scheduling for Latency and Bandwidth
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Solution Overview
Problem
Current microprocessor systems face inefficiencies in memory access bandwidth and latency due to rigid prioritization strategies that fail to account for the varying latency and bandwidth requirements of different memory requests, leading to accumulated prefetches and write requests being bypassed, and poor page management.
Innovation Solution
A memory controller system with two queues that dynamically adjusts the priority of memory requests based on triggers such as matching demand read addresses for prefetches, pending time for isochronous requests, and programmable thresholds for write requests, ensuring optimal scheduling and processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If prefetch requests are assigned low priority to minimize latency for demand read requests, then demand read latency is improved, but prefetch requests accumulate in the queue and bandwidth utilization deteriorates
Solution Approach 1:
The patent implements dynamic priority adjustment where prefetch request priorities are not fixed but change based on queue conditions. When the queue contains only prefetch requests or when demand requests are being processed, prefetch priorities are increased to maintain bandwidth utilization. This dynamic adjustment resolves the contradiction by adapting priority levels to current system state rather than using static low priority for all prefetches.
Solution Approach 2:
The system changes the priority parameter of prefetch requests based on queue composition and processing state. By monitoring queue contents and adjusting prefetch priority levels accordingly, the system optimizes both latency and bandwidth utilization under different operating conditions, resolving the trade-off between these two parameters.
2Loss of time
If write requests are assigned low priority to minimize latency for read requests, then read latency is improved, but write requests accumulate and bandwidth utilization deteriorates
Solution Approach 1:
The patent implements dynamic priority adjustment for write requests based on queue composition. When the queue contains primarily write requests or when read requests are being processed, write priorities are increased to maintain bandwidth utilization. This resolves the contradiction by making write priority adaptive rather than statically low.
Solution Approach 2:
The system changes the priority parameter of write requests based on monitoring queue contents and processing state. By adjusting write priority levels dynamically, the system optimizes both read latency and overall bandwidth utilization under different operating conditions.
3Reliability
If isochronous requests are assigned high priority to meet latency requirements, then latency compliance is improved, but normal read requests are bypassed and bandwidth utilization deteriorates
Solution Approach 1:
The patent implements dynamic priority adjustment for isochronous requests based on queue composition and latency thresholds. When isochronous requests are approaching their latency deadlines or when the queue contains primarily isochronous requests, their priority is increased to ensure compliance. Otherwise, normal read requests are processed first to maintain bandwidth utilization. This resolves the contradiction by making isochronous priority adaptive rather than statically high.
Solution Approach 2:
The system changes the priority parameter of isochronous requests based on monitoring queue contents, latency requirements, and processing state. By adjusting isochronous priority levels dynamically according to actual needs, the system ensures latency compliance while maintaining optimal bandwidth utilization.
4Loss of time
If demand read requests are prioritized over prefetch requests, then demand read latency is improved, but prefetch requests accumulate causing poor page management performance
Solution Approach 1:
The patent implements dynamic priority adjustment where prefetch request priorities are increased when the queue contains primarily prefetch requests or when demand requests are being processed. This prevents prefetch accumulation and maintains good page management performance while still providing low latency for demand reads when they occur.
Data Source
AI summary
A system includes a processor coupled to a memory through a memory controller. The memory controller includes first and second queues. The memory controller receives memory requests from the processor, assigns a priority to each request, stores each request in the first queue, and schedules processing of the requests based on their priorities. The memory controller changes the priority of a request in the first queue in response to a trigger, sends a next scheduled request from the first queue to the second queue in response to detecting the next scheduled request has the highest priority of any request in the first queue, and sends requests from the second queue to the memory. The memory controller changes the priority of different types of requests in response to different types of triggers. The memory controller maintains a copy of each request sent to the second queue in the first queue.