Memory Controller Process Corner Delay Adjustment
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Solution Overview
Problem
The performance of dynamic random-access memory (DRAM) systems is affected by variations in process corners among memory chips, leading to inconsistent data signal transmission and conflicts, which degrade the overall performance of the memory system.
Innovation Solution
A memory system that includes a controller capable of obtaining a parameter characterizing the process corner of each memory chip and adjusting the delay of the read command accordingly, ensuring consistent data signal alignment and improved read/write performance by compensating for differences in data transmission delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory chips with different process corners are used to increase storage capacity, then the storage density is improved, but data signal transmission consistency deteriorates
Solution Approach 1:
The patent applies local quality by assigning different read command delay values to memory chips based on their individual process corners. Each memory chip receives a customized delay adjustment tailored to its specific manufacturing characteristics, ensuring that chips with different process corners (FF, FS, SF, SS) operate with optimized timing parameters that compensate for their unique variations, thereby maintaining data signal consistency across the entire memory system.
Solution Approach 2:
The patent implements parameter changes by dynamically adjusting the read command delay parameter for each memory chip based on its process corner classification. The controller modifies the timing parameter (delay value) according to the specific process characteristics of each chip, transforming a uniform timing approach into a customized parameter set that accounts for manufacturing variations, thus resolving the signal consistency issue while maintaining high storage capacity.
2Device complexity
If uniform read command delay is applied to all memory chips, then the controller complexity is reduced, but data conflicts occur due to process corner variations
Solution Approach 1:
The patent applies preliminary action by pre-classifying memory chips into different process corner categories (FF, FS, SF, SS) and pre-determining the appropriate read command delay values for each category. This preliminary classification and parameter assignment is performed during system initialization or chip identification phase, allowing the controller to subsequently apply the correct delay values without real-time computation, thus maintaining low controller complexity while ensuring reliable data transmission.
3Stability of the object's composition
If read command delay is adjusted for each memory chip, then data signal uniformity is improved, but the control complexity increases
Solution Approach 1:
The patent implements parameter changes by introducing a set of predefined delay values corresponding to different process corner types. The controller selects and applies the appropriate delay parameter based on the identified process corner of each memory chip, transforming a complex continuous adjustment problem into a discrete parameter selection task. This approach maintains data signal uniformity while limiting control complexity through parameterization.
Data Source
AI summary
A memory system includes: a plurality of memory chips, wherein each of the memory chips has a parameter used to characterize a process corner of the memory chip; and a controller, wherein the controller is configured to: obtain the parameter of each of the memory chips, and adjust, based on the parameter, a delay of a read command sent to the memory chip corresponding to the parameter.