Memory Controller Program Depth Map Read Optimization

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Solution Overview

Problem

Non-volatile memory systems face inefficiencies in read operations due to the need to determine the program state of word lines, which often requires additional read operations and flag cells, leading to increased read times.

Innovation Solution

A memory controller manages a program depth bit map to differentiate between lower and upper page program states, allowing for optimized read commands that bypass the need to determine the upper page program state during read operations, thereby reducing read time by eliminating the requirement for flag cells and additional read operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the program state of word lines is determined using additional read operations and flag cells, then the program state can be accurately identified, but the read time increases

Engineering Contradiction:
Improveprogram state identification accuracyVSAvoidread time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent applies preliminary action by pre-determining and storing program state information in a separate metadata structure (program depth map) before read operations. The controller maintains this map during program operations, so when a read operation occurs, the program state is already known from the pre-prepared metadata rather than requiring runtime determination through additional read operations.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces an intermediary metadata structure (program depth map or indicator bits) that mediates between the program operations and read operations. This intermediary stores program state information separately from the actual data, allowing the read operation to quickly retrieve state information without performing additional read operations on the data itself.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If flag cells are used to track upper page program state, then the program state can be monitored, but the device complexity increases

Engineering Contradiction:
Improveprogram state trackingVSAvoidmemory structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the program state tracking function from the main data storage structure by using separate metadata (program depth map or indicator bits stored in dedicated locations). This separation removes the complexity of integrated flag cells from the memory array while maintaining reliable program state tracking through the extracted metadata structure.

Inventive Principle:
Principle #2Taking out (Extraction)

3Measurement precision

If additional read operations are performed to determine program state, then accurate state information is obtained, but productivity decreases

Engineering Contradiction:
Improveprogram state determination accuracyVSAvoidread operation throughput
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

By pre-determining and storing program state information in metadata during program operations, the patent eliminates the need for additional read operations during data retrieval. This preliminary action maintains accurate program state information while maximizing read operation throughput by avoiding runtime state determination.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The metadata structure acts as an intermediary that provides program state information without requiring read operations on the data array. This intermediary enables accurate state determination while maintaining high productivity by decoupling state information retrieval from data retrieval operations.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10169227B2Memory controller and memory system including the same
Publication Date: 2019.01.01 SAMSUNG ELECTRONICS CO LTD
  • US10169227B2 patent drawing
  • US10169227B2 patent drawing
  • US10169227B2 patent drawing

AI summary

An operating method is for a memory device which controls a nonvolatile memory. The operating method includes managing a program depth bit map indicating an upper page program state of each of a plurality of word lines of the nonvolatile memory in response to an external write request, and outputting one of a plurality of different read commands to the nonvolatile memory based on information of the program depth bit map corresponding to a word line to be accessed in response to an external read request.