Memory Controller Progressive Error Detection
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Solution Overview
Problem
Existing memory systems lack an effective method to detect progressive errors in memory devices, which can lead to data corruption and system instability, particularly in non-volatile memory devices where data persistence is critical.
Innovation Solution
A controller with a buffer memory and a central processing unit that generates commands to compare original data with data received from the memory device, using a data comparator to detect defects by identifying uncorrectable errors, thereby determining the health of the memory device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is stored in the memory device without verification, then storage speed is improved, but data integrity deteriorates due to undetected progressive errors
Solution Approach 1:
The patent applies preliminary action by storing original data in a buffer memory before writing to the memory device, and preparing verification commands in advance. This allows the controller to immediately verify data after writing without adding significant delay to the storage operation, thus maintaining storage speed while ensuring data integrity through proactive error detection.
Solution Approach 2:
The patent implements feedback by continuously comparing data read from the memory device with the original stored data through a verification process. When errors are detected, the system generates error information and can trigger corrective actions. This closed-loop feedback mechanism ensures data integrity while allowing high-speed storage operations to proceed, as verification occurs systematically without blocking the main storage flow.
2Reliability
If a verification process is implemented to detect errors, then data integrity is improved, but system complexity increases due to additional components and operations
Solution Approach 1:
The patent applies universality by designing the verification mechanism to serve multiple functions: it detects progressive errors, verifies data integrity, and provides feedback for potential error correction. The same buffer memory and comparison logic are used for both data staging and verification purposes, reducing the need for separate dedicated verification components and thereby limiting the increase in system complexity.
Solution Approach 2:
The controller performs self-verification by comparing its own stored data with data read back from the memory device without requiring external verification systems. This self-service approach allows error detection capability to be improved while avoiding the complexity of adding separate external verification hardware or systems.
3Productivity
If progressive errors are not detected, then device productivity is maintained, but data corruption occurs leading to system instability
Solution Approach 1:
The patent applies skipping by implementing error detection at strategic points in the data flow without requiring complete verification of every single bit at every operation stage. The verification process skips systematically through data blocks, detecting progressive errors efficiently. This allows memory operation speed to be maintained while preventing data corruption that would lead to system instability.
Data Source
AI summary
Embodiments include a controller, a memory system including the controller, and a method of operating the controller. The controller includes a buffer memory configured to store original data. The controller also includes a central processing unit configured to generate a first command for transmitting the original data to a memory device, generate a second command for receiving data from the memory device, and store the data in the buffer memory. The controller further includes a data comparator configured to compare the data stored in the buffer memory with the original data. The central processing unit is further configured to determine whether the memory device is defective according to a comparison result of the data comparator.