Memory Controller Reordering with Push Requests
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Solution Overview
Problem
In digital systems, memory controllers face challenges in maintaining the order of memory operations, leading to situations where older operations are stalled due to reordering, preventing more recent, higher-priority operations from completing despite having already obtained read data, resulting in inefficiencies and delays.
Innovation Solution
The memory controller includes an agent interface unit and memory channel units that allow for the rearrangement of memory operations, with a mechanism to expedite older operations by sending a push request, ensuring that read data from older operations is returned promptly, allowing more recent operations to complete by upgrading their priority or scheduling them faster.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory operations are reordered to improve memory efficiency, then memory access efficiency is improved, but the order of read data returned to the source may be disrupted
Solution Approach 1:
The patent segments the memory operation processing into two independent parts: reordering operations for efficiency at the memory interface, and maintaining original order for data return to the source. This is achieved by tracking operation sequences and using buffering mechanisms that decouple the reordering function from the data return function, allowing both goals to be satisfied simultaneously.
Solution Approach 2:
The patent introduces intermediary buffering mechanisms within the memory controller that temporarily hold read data while maintaining sequence information. These buffers act as mediators between the reordered memory operations and the source that requires ordered data return, allowing the controller to satisfy both the efficiency requirement and the ordering requirement without conflict.
2Stability of the object's composition
If older memory operations are stalled due to reordering, then data order is maintained, but more recent higher-priority operations are delayed from completing
Solution Approach 1:
The patent implements preliminary buffering of read data before it needs to be returned to the source. By preparing and buffering data in advance while tracking operation sequences, the system can quickly return data in the correct order without stalling operations. This preliminary action eliminates the need to wait for older operations to complete before processing newer ones.
Solution Approach 2:
The patent introduces dynamic prioritization mechanisms that can adjust the handling of memory operations based on their characteristics. The system dynamically determines which operations can be accelerated and which must maintain strict ordering, allowing flexible management of the contradiction between maintaining order and preventing delays for high-priority operations.
3Stability of the object's composition
If read data is buffered in the memory controller waiting on earlier transactions, then data order is maintained, but memory efficiency is reduced due to stalled operations
Solution Approach 1:
The patent segments the memory controller functionality into independent modules: one that handles reordering for efficiency, another that manages buffering for order maintenance, and a third that tracks operation sequences. This segmentation allows each module to optimize for its specific function without causing stalls, as the reordering module can operate independently while the buffering module prepares data for ordered return.
Solution Approach 2:
The patent ensures continuous processing of memory operations by implementing mechanisms that prevent stalling. The system continuously reorders operations, continuously buffers data in preparation for return, and continuously tracks sequences, allowing the memory subsystem to maintain high efficiency while still ensuring ordered data return to the source.
Data Source
AI summary
A memory controller, system, and method for accelerating blocking memory operations. A memory controller reorders memory operations so as to maximize efficient use of the memory device bus. When data for a newer memory operation is retrieved from memory and ready to be returned to a source device, the newer memory operation can be held up waiting for an older memory operation to be completed. In response, the memory controller forwards a push request for the older memory operation to a memory channel unit. The memory channel unit then sets a push bit of the older memory operation, which expedites the scheduling of the older memory operation.