Memory Controller Queue Arbiter for Performance Isolation
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Solution Overview
Problem
Existing memory controllers face challenges in efficiently managing and isolating performance across multiple memory partitions in shared memory devices, leading to inefficiencies in command processing and potential bottlenecks due to lack of effective resource allocation and command scheduling.
Innovation Solution
A memory controller with a queue arbiter and command dispatcher that separately and respectively queues memory operation commands for each memory device, using address translation to determine device correspondence and maintaining linked lists for each device, allowing for first-in-first-out order execution and prioritized resource allocation based on work schedules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory operation commands are shared across multiple memory partitions in a shared memory device, then resource utilization is improved, but performance isolation deteriorates
Solution Approach 1:
The patent segments the shared memory device into multiple memory partitions, each with dedicated command queues and associated resources. The memory controller is divided into partition-specific components (command queues, command dispatchers) and shared components (queue arbiter, memory interface). This segmentation allows each partition to have isolated command processing while sharing the physical memory devices, thereby maintaining performance isolation while enabling resource sharing at the device level.
2Device complexity
If commands are processed in a shared queue for multiple memory devices, then device complexity is reduced, but command processing order deteriorates
Solution Approach 1:
The patent implements separate command queues for each memory partition rather than a single shared queue. Each command queue is dedicated to specific memory devices associated with its partition, ensuring that commands are processed in the correct order for each partition. The queue arbiter then manages these segmented queues, selecting which partition's commands to service next, thereby maintaining both processing order and manageable complexity.
Solution Approach 2:
The queue arbiter acts as an intermediary between the multiple partition-specific command queues and the memory devices. It receives commands from various queues, arbitrates their priority and timing, and ensures commands are dispatched in the correct order to the appropriate memory devices. This intermediary layer maintains command processing order without requiring each partition to have complex internal scheduling logic.
3Device complexity
If memory operation commands are dispatched without separate queuing per device, then system complexity is reduced, but performance bottlenecks increase
Solution Approach 1:
The patent segments the command dispatch mechanism into partition-specific command queues, each dedicated to specific memory devices. This allows parallel processing of commands for different partitions simultaneously, eliminating the bottleneck of a single shared queue. Each partition can progress independently through its own command queue, improving overall system throughput while maintaining manageable complexity through the modular queue structure.
Data Source
AI summary
Shared memory device apparatus and related methods are disclosed. An example method includes obtaining memory operation commands. The memory operation commands are received by a command dispatcher in a same order as obtained by the queue arbiter from the host device. The example method further includes separately and respectively queuing the memory operation commands for each of a plurality of memory devices and dispatching the memory operation commands for execution. The example method also includes receiving the dispatched memory operation commands at a plurality of command queues, where each command queue is associated with a respective one of the plurality of memory devices. Each command queue is configured to receive its respective dispatched memory operation commands from the command dispatcher in a same order as received by the dispatcher and provide the received memory operation commands to its respective memory device in a first-in-first-out order.