Memory Controller Queue Control for Shared Memory Access
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Solution Overview
Problem
In parallel computing systems, remote memory accesses to shared objects outside of the cache coherent domain pose significant scalability challenges, particularly for sparse workloads, as existing technologies lack efficient control mechanisms for managing multiple accesses.
Innovation Solution
A memory controller with a lock address list, read and write wait queues, and initiated queues, along with a queue controller that uses Time To Live (TTL) information and lock bit status to selectively manage requests, ensuring efficient and exclusive access to shared memory objects by determining which requests to output, hold, or purge based on lock status and TTL.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If cache is used for local memory access control, then access efficiency within cache coherent domain is improved, but remote memory access scalability deteriorates
Solution Approach 1:
The memory access control is segmented into local cache-coherent domain handling and remote memory access handling. The lock address list segments memory addresses into locked and unlocked regions, allowing different access control mechanisms to be applied to different segments, thereby improving remote access scalability while maintaining local access efficiency.
Solution Approach 2:
The patent introduces intermediary data structures (lock address list, lock bits, wait queues) between processor cores and remote memory to mediate access control. These intermediaries enable efficient coordination of multiple processors accessing shared memory objects without requiring full cache coherence protocols for remote accesses.
2Productivity
If multiple processors access shared memory objects simultaneously, then system parallelism is improved, but access control complexity increases
Solution Approach 1:
The system performs preliminary actions by setting lock bits in the lock address list before processors access shared memory objects. This preliminary locking mechanism establishes access rules in advance, allowing multiple processors to safely access shared memory without complex runtime coordination, thus maintaining high parallelism with simplified control.
Solution Approach 2:
Each processor independently checks the lock address list and lock bits to determine whether it can access a shared memory object, without requiring centralized arbitration. This self-service approach enables processors to autonomously manage their own access rights, reducing access control complexity while supporting multiple simultaneous accessors.
3Reliability
If lock bits are set for all shared memory addresses, then exclusive access control is improved, but memory address space utilization deteriorates
Solution Approach 1:
Instead of uniformly applying lock bits to all memory addresses, the patent applies lock bits selectively only to shared memory object addresses stored in the lock address list. This local quality approach ensures exclusive access control is implemented only where needed (at shared objects), while leaving the rest of the address space unlocked and efficiently usable, thus maintaining both reliability and address space utilization.
Data Source
AI summary
A memory controller is provided for accessing shared memory objects by read and write requests made to a memory. The memory controller includes a list for registering address locations of the shared objects in the memory, and having slots for a lock bit. The memory controller includes a read wait queue and a write wait queue for selectively inputting, outputting, holding, and purging requests. The memory controller includes a read initiated queue and a write initiated queue for selectively inputting and purging requests transferred from the read wait queue and the write wait queue, respectively, upon memory access initiation and completion. The memory controller includes a controller for controlling the wait queues using policies by determining which requests to output, hold, and purge, based on a list entry, a lock bit and TTL information set to each request upon a hold being applied thereto and decremented in each cycle.