Memory Controller Radix Page Translation Latency Reduction
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Solution Overview
Problem
Current address translation methods in computer systems are inefficient due to the high number of exchanges between the processor and memory controller during radix page translation table walks, leading to increased latency and system performance issues.
Innovation Solution
The memory controller performs the entire radix page translation table walk, reducing the number of exchanges between the processor and memory by handling all operations, and transmitting the final page table entry and intermediate addresses back to the processor for caching in the Page Walk Cache.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the processor performs the entire radix page translation table walk, then the address translation can be completed, but the number of exchanges between processor and memory controller increases leading to high latency
Solution Approach 1:
The patent introduces an intermediary structure called the Page Walk Cache (PWC) that stores intermediate addresses during the radix page translation table walk. The memory controller performs the table walk and stores intermediate results in the PWC, reducing the number of exchanges needed between the processor and memory controller for subsequent translations. This intermediary cache acts as a buffer that eliminates redundant communication cycles.
Solution Approach 2:
The memory controller performs the radix page translation table walk in advance and stores the results (intermediate addresses and final page table entries) in the Page Walk Cache before the processor needs them. By performing the translation operation beforehand and caching the results, the system avoids repeated exchanges for the same translation operations, thereby reducing latency.
2Productivity
If multiple exchanges occur between processor and memory controller during address translation, then complete translation can be achieved, but system performance deteriorates
Solution Approach 1:
The Page Walk Cache serves as an intermediary that stores intermediate translation results, allowing the memory controller to batch multiple translation operations and reduce the frequency of exchanges with the processor. This increases system productivity by minimizing communication overhead while maintaining complete translation functionality.
Solution Approach 2:
The patent combines the intermediate address storage and final page table entry storage into a single Page Walk Cache structure. By merging these functions into one cache, the system reduces the number of separate memory operations and exchanges needed, thereby improving overall system performance and reducing translation latency.
3Loss of time
If the memory controller performs the entire radix page translation table walk, then the number of exchanges is reduced, but the memory controller workload increases
Solution Approach 1:
The Page Walk Cache acts as an intermediary data structure that the memory controller can efficiently manage. By using this dedicated cache structure, the memory controller's workload is organized and optimized, making it easier to handle the increased responsibility of performing the entire table walk while minimizing exchanges with the processor.
Data Source
AI summary
Translating virtual addresses to second addresses by a memory controller local to one or more memory devices, wherein the memory controller is not local to a processor, a buffer for storing a plurality of Page Table Entries, or a Page Walk Cache for storing a plurality of page directory entries, the method including by the memory controller: receiving a page directory base and a plurality of memory offsets from the processor; reading a first level page directory entry using the page directory base and a first level memory offset; combining the second level offset and the first level page directory entry; reading a second level page directory entry using the first level page directory entry and the second level memory offset; sending to the processor the first level page directory entry or the second level page directory entry; and sending a page table entry to the processor.