Memory Controller Read Count Recovery for Resistive Memory Reliability

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Solution Overview

Problem

Resistive memory devices face reliability issues due to varying resistance values when read operations are performed, leading to potential data degradation and reduced memory cell reliability.

Innovation Solution

A memory controller manages read operations by tracking read counts in units of subsets, performing recovery operations when a predetermined threshold is reached to maintain resistance distribution and prevent data degradation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If read operations are performed on resistive memory cells, then data can be accessed, but resistance distribution deteriorates and reliability decreases

Engineering Contradiction:
Improvedata access capabilityVSAvoidmemory cell reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent performs recovery operations proactively when read count reaches a threshold value, before significant resistance distribution deterioration occurs. This preliminary action prevents reliability degradation rather than correcting it after damage accumulates, resolving the contradiction between maintaining data access capability and preserving memory cell reliability

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements a feedback mechanism by monitoring read counts for each subset and comparing against threshold values. When the threshold is reached, the system automatically triggers recovery operations. This closed-loop control ensures that read operations are balanced with periodic recovery, maintaining reliability while preserving data access functionality

Inventive Principle:
Principle #23Feedback

2Ease of operation

If read operations are frequently performed, then data accessibility is maintained, but resistance distribution becomes distorted

Engineering Contradiction:
Improvedata accessibilityVSAvoidresistance distribution
Core Design Contradiction:
Ease of operationVSStability of the object's composition

Solution Approach 1:

The patent divides the memory device into multiple subsets, each with independent read count monitoring and threshold management. This segmentation allows selective recovery operations on specific subsets that have reached their threshold, rather than forcing recovery across the entire memory device. This maintains data accessibility in subsets that don't need recovery while restoring resistance distribution in subsets that do

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements periodic recovery operations based on read count thresholds. Instead of continuous monitoring and intervention, the system performs recovery at periodic intervals determined by the threshold values. This periodic action maintains resistance distribution stability while minimizing disruptions to data accessibility

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS11307918B2Memory controller performing recovery operation, operating method of the same, and memory system including the same
Publication Date: 2022.04.19 SAMSUNG ELECTRONICS CO LTD
  • US11307918B2 patent drawing
  • US11307918B2 patent drawing
  • US11307918B2 patent drawing

AI summary

A memory system for performing a recovery operation is provided. A memory system includes a memory device including a plurality of memory cells constituting a plurality of sub-sets, and a memory controller for controlling the memory device. The memory controller controls the memory device to manage a read count indicating a number of read operations performed by the memory device for each of the plurality of sub-sets, and to perform a recovery operation on a sub-set, among the plurality of sub-sets, based on the read count corresponding to the read count. Each of a plurality of sub-sets includes a plurality of pages. Each of the plurality of pages is a unit in which a read operation is performed in the plurality of memory cells.