Memory Controller Read Count Table for Data Rearrangement
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Solution Overview
Problem
The existing data storage devices face performance issues due to time-consuming lookup operations in mapping tables as the memory size increases, leading to decreased read speed.
Innovation Solution
A data processing method that involves a memory controller managing a read count table to identify frequently accessed sub-regions and rearranging data within these sub-regions to contiguous physical addresses, improving access efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the mapping table size increases to support larger memory capacity, then the memory device can store more data, but the lookup time increases enormously
Solution Approach 1:
The patent divides the mapping table into multiple segments or partitions, each handling a specific range of logical addresses. This segmentation allows the lookup operation to be performed on smaller subsets of the mapping table rather than searching the entire table, significantly reducing lookup time while maintaining support for large memory capacity.
Solution Approach 2:
The patent introduces a hierarchical addressing structure with multiple dimensions - including logical address, physical address, and intermediate mapping indices. This dimensional approach enables the system to navigate the mapping table more efficiently by using index-based access patterns rather than linear search, thereby reducing lookup time in proportion to the increase in memory capacity.
2Adaptability or versatility
If the mapping table is searched sequentially to find physical addresses, then all logical addresses can be accessed, but the read speed decreases due to time-consuming lookup operations
Solution Approach 1:
The patent pre-organizes the mapping table structure during initialization and data storage operations, creating optimized index structures and maintaining sorted orderings. This preliminary organization enables subsequent read operations to quickly locate physical addresses without performing exhaustive sequential searches, thereby improving read speed while preserving full address access capability.
Solution Approach 2:
The patent replaces the mechanical sequential search process with algorithmic lookup methods including binary search, hash-based indexing, or tree-based search structures. These computational approaches substitute the linear time complexity of sequential searching with logarithmic or constant time complexity operations, significantly increasing read speed while maintaining adaptability to access any logical address.
Data Source
AI summary
A data storage device includes a memory device including multiple memory blocks corresponding to multiple sub-regions and a memory controller. The memory controller updates content of a read count table in response to a read command with a transfer length greater than 1 for designating more than one logical address to be read. The read count table includes multiple fields recording a read count associated with one sub-region and content of the read count table is updated by increasing the read count(s) associated with the sub-region(s) that logical addresses designated in the read command belong to. The memory controller selects at least one sub-region according to the content of the read count table and performs a data rearrangement procedure to move data of the logical addresses belonging to the selected at least one sub-region to a first memory space of the memory device having continuous physical addresses.