Memory Controller Read Optimization via Count-Based Table Management
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Solution Overview
Problem
The existing memory devices experience degraded access performance due to the need to frequently update conversion tables in volatile memory, which leads to increased read requests from the host, causing inefficiencies in accessing nonvolatile memory.
Innovation Solution
A memory device architecture that includes a nonvolatile memory and a volatile memory with a controller that manages conversion tables by reading, comparing, and rewriting count values to optimize data table entries, allowing for improved read performance by prioritizing frequently accessed logical addresses in the volatile memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conversion tables are updated in volatile memory at each random access from host, then logical to physical address conversion is enabled, but access performance of storage device is degraded
Solution Approach 1:
The system pre-loads conversion tables from nonvolatile memory into volatile memory before they are needed for address conversion operations. By having the conversion tables ready in advance in the faster volatile memory, the system avoids the performance penalty of accessing nonvolatile memory during actual data operations, thus resolving the contradiction between enabling address conversion and maintaining access performance.
2Speed
If volatile memory is used as cache memory, then random access speed is improved, but memory device complexity increases
Solution Approach 1:
The volatile memory is designed to serve multiple functions: it acts as both cache memory for improving random access speed and as storage for conversion tables for address conversion operations. By making the volatile memory multi-functional, the system achieves speed improvement without proportionally increasing overall device complexity, as the same hardware resource fulfills multiple roles.
Data Source
AI summary
According to one embodiment, a memory device includes a nonvolatile memory, a volatile memory, and a controller which writes a first data table including a first data group including a first logical address corresponding to a first physical and a first count value and a second data group including a second logical address corresponding to a second physical address and a second count value, to the volatile memory, reads the first data table when a third logical address is requested to be read, compares the first count value and the second count value with each other, and rewrites the first data group or the second data group to a third data group including a third logical address based on a result of the comparison.