Memory Controller Read Disturb Mitigation via Selective Refresh
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Solution Overview
Problem
NAND-type flash memory devices face limitations in the number of writes/erasures and readouts due to degradation of the oxide film around floating gates and the phenomenon of read disturb, which leads to data degradation and increased readout errors, and existing refresh processing methods are complex and inefficient.
Innovation Solution
A memory controller with a logical-physical address conversion table, an access number storing section, a storage state checking section, and a refresh processing section that performs refresh processing on memory cells at predetermined intervals to restore data storage states, thereby preventing read disturb and maintaining data reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If refresh processing is performed on all memory cells to prevent read disturb, then data reliability is improved, but the number of writes/erasures increases causing memory cell degradation
Solution Approach 1:
The patent applies local quality by performing refresh processing selectively on specific memory cells that require it, rather than uniformly on all memory cells. The memory controller identifies memory cells with degraded storage conditions and applies refresh processing only to those cells, thereby preventing read disturb while avoiding unnecessary writes/erasures on healthy cells and extending overall memory cell lifespan.
2Reliability
If refresh processing is performed frequently to prevent read disturb, then data reliability is improved, but processing overhead and energy consumption increase
Solution Approach 1:
The patent implements feedback by continuously monitoring the storage conditions of memory cells and using this information to dynamically control refresh processing. The memory controller checks storage conditions and performs refresh processing only when degradation is detected, creating a feedback loop that adjusts refresh frequency based on actual memory cell state, thereby reducing unnecessary processing overhead and energy consumption while maintaining data reliability.
Solution Approach 2:
The patent applies periodic action by performing refresh processing at intervals based on monitored storage conditions rather than continuously or at fixed time intervals. The memory controller periodically checks storage conditions and triggers refresh processing only when necessary, optimizing the balance between data reliability and processing efficiency.
3Duration of action of stationary object
If wear leveling is performed to distribute writes/erasures evenly, then memory cell lifespan is extended, but the complexity of address management increases
Solution Approach 1:
The patent applies preliminary action by pre-establishing a mapping structure between logical addresses and physical addresses before wear leveling operations. The memory controller maintains a conversion table that maps logical addresses to physical addresses, allowing wear leveling to redistribute data across memory cells without requiring complex real-time address translation, thereby extending memory cell lifespan while managing address complexity through pre-planned mappings.
Data Source
AI summary
A memory controller includes logical-physical address conversion table, an access number storing section configured to store the number of accesses to read out data from a memory cell in association with a logical address, a storage state checking section configured to check a storage state of data stored in the memory cell at every predetermined number of accesses, and a refresh processing section configured to perform refresh processing to restore the data stored in the memory cell if the storage state of the data is in a predetermined degraded state.