Memory Controller Read Disturb Mitigation via Count-Based Refresh
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Solution Overview
Problem
NAND flash memories experience unintended data rewriting due to repeated read operations, known as the 'read disturb phenomenon', which existing solutions cannot effectively address without relying on specific cell configurations.
Innovation Solution
A memory controller that determines a refresh target area based on read counts to proactively rewrite data, using methods such as saving data in a temporary memory, copying data to another area, or erasing data blocks to prevent unintended rewriting, allowing for flexible application across various memory configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If data is repeatedly read out from NAND flash memory, then data access is enabled, but unintended data rewriting occurs due to read disturb phenomenon
Solution Approach 1:
The memory controller performs preliminary actions by monitoring read counts and proactively rewriting data in areas that have been read a predetermined number of times or more, before actual data corruption occurs. This preventive approach addresses the read disturb phenomenon by refreshing data in advance, thereby maintaining data integrity while allowing continuous read access.
Solution Approach 2:
The system implements a feedback mechanism where the memory controller continuously monitors the number of read operations for each memory area. Based on this feedback information, the controller determines which areas require rewriting and executes the rewrite operation accordingly, creating a closed-loop system that adapts to actual read patterns and prevents data corruption.
2Reliability
If conventional read disturb prevention methods are used, then data integrity is protected in specific cell configurations, but the solution cannot be applied to other memory configurations
Solution Approach 1:
The invention implements a universal solution by monitoring read counts at the memory area level rather than relying on specific cell configuration characteristics. The memory controller applies the same read count monitoring and proactive rewriting logic across different memory configurations (SLC, MLC, TLC, etc.), making the solution adaptable and applicable to various NAND flash memory types without requiring configuration-specific adjustments.
Data Source
AI summary
A memory controller for controlling data access to a memory comprises a refresh controller. A read count memory part included in the refresh controller counts the number of read operations on each page of the memory and stores the read count therein. If the read count for any page exceeds a predetermined number, the refresh controller rewrites data stored in this page into the memory.