Memory Controller Read Error Processing for Temporary Read Errors
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Solution Overview
Problem
Current memory systems face challenges with temporary read errors (TRE) when transitioning from a non-operating state to an operating state, leading to high read failure bit counts and affecting system performance, particularly due to semiconductor channel grain boundary trap occupancy changes and charge trapping/storage layer effects.
Innovation Solution
The implementation of a memory system with a memory controller that performs part or all of a read error processing flow for at least two times, including pseudo read operations and error correction operations, to mitigate TRE by optimizing the operating logic and manufacturing process, reducing semiconductor channel thickness, and using machine learning for processing time determination based on temperature.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the memory system transitions from non-operating state to operating state, then the system becomes available for normal operations, but temporary read errors occur due to semiconductor channel grain boundary trap occupancy changes
Solution Approach 1:
The patent applies preliminary action by performing a pseudo read operation before the actual read operation when the memory system transitions from non-operating to operating state. This preliminary pseudo read mitigates the temporary read errors caused by grain boundary trap occupancy changes, ensuring that the semiconductor channel is properly activated and traps are filled before normal read operations commence, thus preventing high read failure bit counts in subsequent operations
2Reliability
If read error processing flow is performed multiple times, then temporary read errors are reduced, but processing time and system complexity increase
Solution Approach 1:
The patent applies partial action by performing the read error processing flow (including pseudo read operations) selectively only when the memory system transitions from non-operating to operating state, rather than executing it continuously or excessively. This targeted approach reduces temporary read errors at the critical transition point without incurring unnecessary processing time penalties during normal operations, thus optimizing the balance between reliability improvement and time loss
3Quantity of substance
If semiconductor channel thickness is reduced, then storage density increases, but grain boundary trap effects and temporary read errors become more significant
Solution Approach 1:
The patent applies parameter changes by modifying the operational parameters (applying pseudo read operations with specific voltage conditions) to compensate for the increased grain boundary trap effects resulting from reduced semiconductor channel thickness. This allows the system to maintain high storage density achieved through thin channels while mitigating the reliability degradation caused by enhanced trap occupancy changes during state transitions
Data Source
AI summary
A memory system and operation method thereof are provided according to implementations of this disclosure. The memory system comprises: at least one memory device and a memory controller coupled to the at least one memory device. The memory controller is configured to: perform part or all of a read error processing flow for at least two times, in response to a failure of a first read operation when performing a read operation on a memory region in the memory device.