Memory Controller Read-Level Hierarchy for Lower Read Failures
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Solution Overview
Problem
As the capacity of non-volatile memory devices increases, the size and cost of high-speed memory required to store read level (RL) information for reducing data failures also increase, leading to inefficiencies.
Innovation Solution
A memory controller manages RL information by storing it in super block and chip units, allowing for optimized read operations across multiple memory chips, reducing the likelihood of data failures while minimizing resource usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If read level information is stored for each read unit of memory cells to reduce data failures, then reliability improves, but the size and cost of high-speed memory increases
Solution Approach 1:
The patent segments read level information storage into two hierarchical levels: super block read level information stored in a first memory for multiple memory chips, and chip read level information stored in a second memory for individual memory chips. This segmentation allows the system to reduce the total amount of read level information that must be stored in expensive high-speed memory while maintaining the ability to handle data failures at both super block and chip levels.
Solution Approach 2:
The patent applies local quality by differentiating the storage requirements for different units of memory organization. Super block read level information is stored with broader scope across multiple chips, while chip-specific read level information is stored locally for individual chip operations. This allows optimization of high-speed memory usage by storing only essential information in the first memory while keeping detailed information in the second memory.
2Speed
If read level information is stored in a single memory structure, then access speed is maintained, but memory cost and resource usage increase
Solution Approach 1:
The patent divides the read level information storage system into two separate memory structures: a first memory for super block read level information and a second memory for chip read level information. This segmentation enables the system to optimize for both speed and cost by storing frequently accessed super block information in the first memory while keeping detailed chip information in the second memory, reducing the total capacity required in expensive high-speed memory.
Solution Approach 2:
The patent introduces a hierarchical dimension to read level information storage by organizing memory resources into two levels: super block level (first memory) and chip level (second memory). This dimensional organization allows the system to access read level information efficiently while minimizing the amount of expensive high-speed memory required, as not all read level information needs to be available at the fastest access level.
Data Source
AI summary
An operating method of a memory controller is provided. The method includes: in a first super block including first blocks of memory chips, storing a first read level with respect to a first block in a first memory as first super block read level (RL) information; storing the first read level in a second memory as first chip RL information corresponding to the first memory chip; during the read operation on the first blocks included in the first super block, controlling the read operation based on the first super block RL information stored in the first memory; and based on a failure occurring in data read from the first block of the first memory chip by using the first super block RL information, controlling the read operation on the first block of the first memory chip based on the first chip RL information stored in the second memory.