Memory Controller Read Retry Data Reliability Check
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Solution Overview
Problem
In memory systems, existing technologies face challenges in ensuring data reliability during read operations, leading to potential errors and inefficiencies in data transmission and error correction, particularly in portable electronic devices where mechanical parts are absent and high data access speeds are required.
Innovation Solution
A memory system and operating method that involve a memory device and a memory controller performing error correction operations and read retry operations based on specific data ranges, ensuring only reliable data is output, with the controller controlling the memory device to re-perform read operations using different voltages until the data falls within a set reliability range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If read retry operations are performed without verifying data reliability, then data access speed is improved, but data reliability deteriorates
Solution Approach 1:
The patent applies preliminary action by checking data reliability (number of specific data within set range) before outputting data from read retry operations. The memory device determines whether read data meets reliability criteria prior to transmission to the memory controller, preventing unreliable data from being processed further. This ensures data reliability is maintained while enabling fast read retry operations.
2Reliability
If all read data is transmitted to the memory controller for error correction, then data reliability is improved, but system efficiency deteriorates
Solution Approach 1:
The patent extracts only the necessary reliability verification step from the data transmission process. Instead of transmitting all read data for error correction, the memory device performs a preliminary check by determining whether the number of specific data falls within a set range. Only data passing this extraction criterion is transmitted to the memory controller, eliminating unnecessary error correction operations and improving system efficiency while maintaining reliability.
Solution Approach 2:
The patent applies partial action by implementing a partial error correction mechanism. Rather than performing full error correction on all transmitted data, the system performs a partial check at the memory device level (verifying data range criteria) before transmission. This partial verification reduces the burden on the memory controller and improves overall system efficiency while still ensuring data reliability.
3Reliability
If read retry operations are performed with multiple voltage adjustments, then data reliability is improved, but operation complexity increases
Solution Approach 1:
The patent applies self-service by enabling the memory device to autonomously perform reliability verification of read data. The memory device independently determines whether the number of specific data is within the set range and decides whether to transmit data to the memory controller. This self-service capability at the memory device level reduces the operational complexity burden on the memory controller while maintaining high data reliability through multiple voltage-adjusted read retry operations.
Data Source
AI summary
A memory system includes a memory device configured to store data, and read and output the stored data in a read operation, and a memory controller configured to perform an error correction operation on the data received from the memory device in the read operation and control the memory device to perform a read retry operation, based on the result of the error correction operation. The memory device outputs the data read in the read retry operation to the memory controller when the number of specific data, among data read in the read retry operation, is in a set range. Only reliability-ensured data in the read retry operation is output to the memory controller. Thus, the number of times of outputting data to the memory controller can be decreased, and the number of times where the memory controller performs an error correction operation can be decreased.