Memory Controller Queues for Subsequent-Read Transfer Hints

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Solution Overview

Problem

Existing memory systems lack efficient methods to generate and provide hint information on data transfer to improve operational speed and efficiency, particularly in high-speed flash memory devices like UFS interfaces.

Innovation Solution

A memory controller with an initiation queue, completion queue, and data package generator that generates hint information based on the status of read data in these queues, creating data packets with both read data and predictive information on subsequent data for faster transfer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If hint information on subsequent data is generated and included in data packets, then data transfer efficiency and operational speed are improved, but device complexity increases due to the need for initiation queues, completion queues, and data package generator

Engineering Contradiction:

Improvedata transfer efficiencyVSAvoidmemory controller structure

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The memory controller generates hint information about subsequent data before the actual data transfer completes. By using the initiation queue to track data preparation status and the completion queue to monitor transfer completion, the system can proactively prepare and include hints in data packets, allowing the host to anticipate and prepare for upcoming data transfers, thereby improving overall transfer efficiency

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The memory controller is divided into functional segments: an initiation queue for tracking data preparation status, a completion queue for monitoring transfer completion, and a data package generator for creating packets with hints. This segmentation allows each component to operate independently and efficiently, managing complexity through modular functional division

Inventive Principle:

Principle #1Segmentation

2Speed

If hint information is provided in data packets, then operational speed is improved, but the data packet structure becomes more complex

Engineering Contradiction:

Improveoperational speedVSAvoiddata packet structure

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The hint information is nested within the existing data packet structure rather than creating a completely new structure. The data packet includes both the actual read data and the hint information about subsequent data, allowing the host to process both current and upcoming data transfers more efficiently without requiring a fundamental redesign of the packet format

Inventive Principle:

Principle #7Nested doll (Nesting)

Data Source

PatentUS20250335130A1Memory controller, memory system, and operating method of memory system

Publication Date: 2025.10.30 SK HYNIX INC

AI summary

A memory controller includes: an initiation queue for storing identification information corresponding to read data of which preparation for transfer to outside the memory controller has started, in response to read requests received from the outside; a completion queue for storing identification information corresponding to read data of which preparation for transfer to the outside is complete; and a data package generator for generating hint information, based on information stored in the initiation queue and the completion queue, generating a data packet including the hint information and first read data of which preparation for transfer is complete, and transferring the data packet to the outside. The hint information may include information on second read data to be transferred to the outside subsequently to the first read data.