Memory Controller Read Voltage Adaptation for Error Correction

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Solution Overview

Problem

Current memory systems face challenges in rapidly setting an optimal read voltage during read operations, leading to inefficiencies and increased latency due to the slow write and read speeds of nonvolatile memory devices.

Innovation Solution

A controller is designed with an error correction circuit, read retry range setting circuit, and read voltage setting circuit to dynamically adjust the read voltage based on error bit numbers and error correction capability, allowing for adaptive read retry operations in memory systems.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Stability of the object's composition

If a nonvolatile memory device is used for data storage, then data retention stability is improved, but write and read speeds deteriorate

Engineering Contradiction:
Improvedata retention stabilityVSAvoidwrite and read speeds
Core Design Contradiction:
Stability of the object's compositionVSSpeed

Solution Approach 1:

The controller performs preliminary actions by checking the error correction capability of the ECC circuit before conducting read operations, and pre-configures the read retry range and read voltage settings based on this check. This preliminary configuration enables faster read operations by avoiding runtime voltage search and retry delays, thus improving read speed while maintaining the stability advantage of nonvolatile memory

Inventive Principle:
Principle #10Preliminary action

2Device complexity

If a fixed read voltage is used for read operations, then device complexity is reduced, but data retrieval efficiency deteriorates due to inability to adapt to error conditions

Engineering Contradiction:
Improvevoltage control complexityVSAvoiddata retrieval efficiency
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The system transitions from a fixed read voltage approach to a dynamic voltage selection mechanism. The controller dynamically adjusts the read voltage based on real-time error bit numbers detected during read operations and the predetermined read retry range. This dynamic adaptation improves data retrieval efficiency by selecting optimal voltages for different error conditions while maintaining manageable complexity through automated control logic

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system implements a feedback mechanism where the error correction circuit provides error bit number information back to the controller, which then adjusts the read voltage accordingly. This closed-loop feedback enables the system to adapt to varying error conditions and optimize read operations, significantly improving data retrieval efficiency compared to fixed voltage approaches

Inventive Principle:
Principle #23Feedback

3Reliability

If read retry operations are performed with multiple voltage attempts, then data retrieval reliability is improved, but operation time increases

Engineering Contradiction:
Improvedata retrieval reliabilityVSAvoidoperation time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The controller performs preliminary configuration of the read retry range and voltage settings based on the error correction capability check before actual read operations. This preconfiguration enables faster retry operations by eliminating runtime voltage search and setup delays, thus reducing the time loss associated with retry operations while maintaining improved data retrieval reliability

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system changes operational parameters (read voltage and read retry range) based on the error correction capability and detected error bit numbers. By dynamically adjusting these parameters, the system achieves higher data retrieval reliability through adaptive retry operations while minimizing time loss through intelligent parameter selection that avoids unnecessary retry attempts

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11004504B2Controller, memory system including the controller, and operating method of the memory system
Publication Date: 2021.05.11 SK HYNIX INC
  • US11004504B2 patent drawing
  • US11004504B2 patent drawing
  • US11004504B2 patent drawing

AI summary

A controller comprises an error correction circuit configured to check an error bit number of error bits in the read data and correct the error bits; a read retry range setting circuit configured to reset a preset read retry range with respect to the read data, and set a new read retry range based on the error bit number and an error correction capability of the error correction circuit; a read voltage setting circuit configured to reset the set read voltage and set, as a new read voltage, a voltage among a plurality of voltages of the reset read retry range, corresponding to the new read retry range; and a flash control circuit configured to control the memory device to perform a read retry operation on the stored data, using the new read voltage.