Memory Controller Read Voltage Optimization for Storage Overhead

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Solution Overview

Problem

Data storage devices face unnecessary decoding and computing overhead during read operations due to failed read attempts, which increase operational and computational complexity.

Innovation Solution

A memory controller is implemented with an optimum read voltage retry controller and read fail controller to calculate and apply an optimum read voltage for failed read operations, reducing overhead by selectively performing soft decoding and retry operations based on the physical address of failed read operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If conventional read operations are performed without voltage optimization, then read speed is maintained, but decoding overhead and computational complexity increase due to failed read attempts

Engineering Contradiction:
Improvedecoding overheadVSAvoidread operation time
Core Design Contradiction:
Device complexityVSLoss of time

Solution Approach 1:

The system performs preliminary actions by calculating and storing optimal read voltages before actual read operations. When a read failure occurs, the pre-calculated optimal voltage for that specific physical address is applied immediately, avoiding the need for complex real-time decoding and voltage adjustment procedures.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The invention changes the read voltage parameter dynamically based on the physical address of the memory location. By adjusting the voltage parameter to its optimal value for each specific address, the system resolves read failures without requiring extensive decoding operations, thereby reducing computational complexity.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If complex recovery algorithms are applied to all failed read operations, then data recovery reliability improves, but computational burden increases

Engineering Contradiction:
Improvedata recovery reliabilityVSAvoidcomputational burden
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The system applies local quality by treating each physical address uniquely with its own optimal read voltage characteristic. Instead of applying uniform complex recovery algorithms to all failed reads, the system locally optimizes each address with its specific voltage parameter, achieving high recovery reliability with minimal computational effort.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The invention creates a copy or mapping of optimal voltages for each physical address in advance. This pre-computed voltage map serves as a lookup table that provides immediate solutions for read failures, eliminating the need to run energy-intensive recovery algorithms during actual read operations.

Inventive Principle:
Principle #26Copying

3Reliability

If optimal read voltage is calculated for each failed read operation, then read success rate improves, but operational overhead increases

Engineering Contradiction:
Improveread success rateVSAvoidoperational overhead
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The optimal read voltage calculation is performed as a preliminary action during system initialization or idle periods, not during actual read operations. This pre-computation stores voltage solutions in advance, so when read failures occur, the system simply retrieves the pre-calculated voltage without performing additional complex operations.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11393538B2Data storage device and method of operating the same
Publication Date: 2022.07.19 SK HYNIX INC
  • US11393538B2 patent drawing
  • US11393538B2 patent drawing
  • US11393538B2 patent drawing

AI summary

A data storage device having a reduced overhead according to an embodiment of the disclosed technology may include a plurality of memory chips each including a plurality of planes, and a memory controller configured to perform recovery algorithms that recover data corresponding to failed read operations among read operations performed on the plurality of memory chips, and the memory controller may generate a read voltage to be used in a first recovery algorithm using an address related to a selected read operation among the failed read operations and perform the first recovery algorithm on a memory location associated with the failed read operations using the read voltage.