Memory Controller Real-Time Testing via Command Reconfiguration
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Solution Overview
Problem
The increasing integration of memory systems leads to higher costs and times for testing, with existing fault detection algorithms being either inefficiently short or excessively long, and built-in self-testers becoming redundant and increasing chip size when embedded.
Innovation Solution
A memory controller with a built-in self-tester, scheduler, and main controller that allows real-time testing by reconfiguring command execution orders and using a switch to direct test commands, enabling direct user input and shared control for both memory operations and testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a built-in self-tester is embedded into a semiconductor chip, then the test cost decreases, but the size of the semiconductor chip increases and the BIST becomes redundant after the test
Solution Approach 1:
The main controller is designed to perform dual functions: controlling normal memory operations and functioning as a BIST controller for testing. The controller receives both normal commands from a scheduler and test commands from a BIST unit, managing memory operations and test operations through a unified command interface. This eliminates the need for a separate dedicated BIST controller, reducing chip size while maintaining testing capability.
2Ease of manufacture
If a BIST is embedded into a semiconductor chip, then the test cost decreases, but the BIST becomes redundant after the test
Solution Approach 1:
The main controller serves as both a normal memory controller and a BIST controller. During normal operation, it executes commands from the scheduler; during testing, it executes test commands from the BIST unit. This multi-functional design allows the controller to be reused for both operational control and testing purposes throughout the product lifecycle, eliminating redundancy.
Solution Approach 2:
The controller dynamically switches between normal operation mode and test mode based on the type of command received. The switch component directs commands from either the scheduler or the BIST unit to the main controller based on a control signal, enabling the system to adapt its behavior depending on whether it is performing normal memory operations or testing.
3Measurement precision
If external apparatus is used for testing a semiconductor chip, then the test accuracy is high, but the test cost increases
Solution Approach 1:
The semiconductor chip performs self-testing through the BIST unit that generates test commands and the main controller that executes them. The chip tests itself without requiring external testing apparatus, maintaining test accuracy while significantly reducing testing costs. The BIST unit creates test patterns and the main controller processes test commands, enabling autonomous testing capability.
Data Source
AI summary
A memory controller according to an aspect of the present invention includes a buffer configured to store an operation command table including operation commands entered by a user, a BIST (built-in self-tester) controller configured to generate a pointer pointing to an operation command, a command and address generator configured to decode the operation command corresponding to the pointer among the operation commands to generate first memory commands, a command and address queue comprising queues for storing the first memory commands, and a command requester configured to output a test command including first operation command information for the generation of a memory command output from a first queue included in the queues among the memory command, location information of the first queue, and the operation commands.