Memory Controller Rearranging Sequential Data for Read Performance

Solution Overview

Problem

Performance degradation of read operations for sequential data occurs after multiple copy operations in semiconductor memory devices, leading to inefficiencies due to randomized data storage.

Innovation Solution

A controller with a rearranging unit that reorders sequential data based on sequence-information, ensuring data is written and read in a sequential manner, even during copy operations, to maintain efficient access speeds.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple copy operations are performed for sequential data in semiconductor memory devices, then data can be transferred between memory blocks, but read operation performance degrades due to randomized data storage

Engineering Contradiction:

Improvedata transfer capabilityVSAvoidread operation speed

Core Design Contradiction:

ProductivityVSSpeed

Solution Approach 1:

The controller performs preliminary rearrangement of sequential data before copy operations are completed. By detecting when sequential data is stored in random order and proactively rearranging it according to sequence information, the system prevents performance degradation before it occurs during subsequent read operations.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The controller uses sequence information as feedback to detect and correct random data storage patterns. By monitoring the storage state of sequential data and comparing it against the expected sequence order, the system identifies when rearrangement is needed and executes it to maintain optimal read performance.

Inventive Principle:

Principle #23Feedback

2Adaptability or versatility

If sequential data is stored in random order after copy operations, then memory flexibility is improved, but access time increases

Engineering Contradiction:

Improvememory storage flexibilityVSAvoiddata retrieval time

Core Design Contradiction:

Adaptability or versatilityVSLoss of time

Solution Approach 1:

The controller performs preliminary rearrangement of sequential data before copy operations are completed. By detecting when sequential data is stored in random order and proactively rearranging it according to sequence information, the system prevents performance degradation before it occurs during subsequent read operations.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The controller uses sequence information as feedback to detect and correct random data storage patterns. By monitoring the storage state of sequential data and comparing it against the expected sequence order, the system identifies when rearrangement is needed and executes it to maintain optimal read performance.

Inventive Principle:

Principle #23Feedback

3Productivity

If data rearrangement is performed, then read operation efficiency is maintained, but controller complexity increases

Engineering Contradiction:

Improveread operation efficiencyVSAvoidcontroller structure complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The controller integrates multiple functions into a single unit that handles both data copying and rearrangement operations. The same controller architecture that manages normal data transfer also detects random storage patterns and executes rearrangement operations, eliminating the need for separate dedicated rearrangement hardware and reducing overall system complexity.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS10489078B2Controller keeping a sequence of data and operating method thereof

Publication Date: 2019.11.26 SK HYNIX INC

AI summary

A controller includes a memory suitable for storing first data read from first memory blocks of a first super memory block included in a memory device; a rearranging unit suitable for rearranging the first data stored in the memory based on sequence-information of the first data stored in the memory; and a processor suitable for controlling the memory device to write the rearranged first data in a second super memory block of the memory device.