Memory Controller Address Verification via Redundant Storage

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Solution Overview

Problem

In memory systems with large nonvolatile memory capacities, the enormous data amount of the address translation table can degrade read performance, and existing solutions that shift address resolution load to the host may still face issues with incorrect address information.

Innovation Solution

A memory system that includes a mechanism for the controller to verify the validity of address information received from the host by comparing the logical address specified in the read command with the logical address stored in the redundant area of the nonvolatile memory, allowing for correct data retrieval even if the host-provided address information is incorrect.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the host holds part of the address translation table and performs address resolution, then the load of address resolution is removed from the memory system and read performance is improved, but incorrect address information may be provided by the host

Engineering Contradiction:
Improveread performanceVSAvoidaddress information validity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The controller verifies the validity of address information provided by the host by comparing it with address information stored in the nonvolatile memory. This feedback mechanism allows the system to detect and correct incorrect address information while maintaining the performance benefits of host-based address resolution.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The nonvolatile memory acts as an intermediary that stores reference address information. The controller uses this stored information to verify the host-provided address information, serving as a mediator between the host and the data storage to ensure accuracy without bottlenecking performance.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If the controller verifies address information by comparing with stored logical addresses, then the validity of address information is determined, but read performance may be degraded due to additional verification steps

Engineering Contradiction:
Improveaddress information validityVSAvoidread performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The controller performs address verification before data retrieval operations. By preliminarily checking the validity of address information and correcting any errors beforehand, the system ensures that subsequent data read operations can proceed efficiently without repeated verification steps or error corrections during the data transfer.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12298899B2Memory system and address verification method
Publication Date: 2025.05.13 KIOXIA CORP
  • US12298899B2 patent drawing
  • US12298899B2 patent drawing
  • US12298899B2 patent drawing

AI summary

According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller is capable of communicating with a host and controls the nonvolatile memory. The controller determines validity of first information for a logical address, when the controller receives, from the host, a read command including the logical address and the first information, the logical address indicating a logical location on the nonvolatile memory, the first information being associated with the logical address.