Memory Controller Refresh Abort Mechanism
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As memory capacity increases, the time required for refresh operations in volatile memory devices like DRAM grows, leading to increased unavailability and reduced bandwidth, causing transaction stalls and impacting isochronous bandwidth requirements.
Innovation Solution
Implementing a refresh abort mechanism that allows the memory controller to prematurely end an active refresh operation, enabling immediate access to memory resources, thereby controlling refresh timing and reducing unavailability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory capacity is increased, then storage capacity is improved, but refresh time increases and bandwidth decreases
Solution Approach 1:
The patent segments the refresh operation into multiple independent row refreshes within a single refresh command. Instead of refreshing all rows sequentially in one long operation, the memory device divides the refresh into parallel segments that can be interleaved with data accesses, thereby maintaining high memory capacity while preserving bandwidth availability.
2Reliability
If refresh operation is performed on entire rank, then data validity is maintained, but memory resources become unavailable for read and write accesses
Solution Approach 1:
The refresh operation is segmented into individual row refreshes that can be performed independently and in parallel with data accesses. This segmentation allows the memory to maintain data validity across all rows while minimizing the time any single row is unavailable, as other rows remain accessible for read and write operations.
Solution Approach 2:
The memory device performs preliminary actions by initiating multiple row refreshes in advance and interleaving them with data accesses. The refresh operations are scheduled and executed in a manner that anticipates access patterns, ensuring data validity is maintained before actual accesses occur, thereby reducing perceived unavailability time.
3Productivity
If refresh execution time increases, then more rows are refreshed per command, but transaction stalls increase
Solution Approach 1:
The patent segments the long refresh operation into multiple shorter row refreshes that can be executed in parallel with data transactions. This segmentation breaks down the monolithic refresh execution into manageable segments that do not cause prolonged transaction stalls, while still achieving comprehensive row coverage through multiple commands.
Solution Approach 2:
The memory device dynamically adjusts refresh execution by interleaving row refreshes with data accesses based on real-time transaction patterns. This dynamic approach allows the system to optimize between refresh completion and transaction availability, reducing stalls by adapting refresh timing to actual workload conditions.
4Reliability
If refresh command is sent frequently, then data validity is maintained, but bandwidth consumption increases
Solution Approach 1:
The refresh functionality is segmented into two modes: automatic refresh that operates independently to maintain data validity, and manual refresh that allows controlled execution. This segmentation enables the system to maintain reliability through automatic operations while reducing bandwidth consumption by allowing selective manual refresh execution based on actual needs.
Solution Approach 2:
The memory device performs self-service by automatically executing refresh operations without requiring frequent controller intervention. The automatic refresh mechanism monitors and maintains data validity independently, reducing the bandwidth overhead associated with controller-managed refresh commands while ensuring data remains valid.
Data Source
AI summary
A memory subsystem enables a refresh abort command. A memory controller can issue an abort for an in-process refresh command sent to a memory device. The refresh abort enables the memory controller to more precisely control the timing of operations executed by memory devices in the case where a refresh command causes refresh of multiple rows of memory. The memory controller can issue a refresh command during active operation of the memory device, which is active operation refresh as opposed to self-refresh when the memory device controls refreshing. The memory controller can then issue a refresh abort during the refresh, and prior to completion of the refresh. The memory controller thus has deterministic control over both the start of refresh as well as when the memory device can be made available for access.