Memory Controller Refresh Logic for Adjacent Cell Interference
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Solution Overview
Problem
Existing memory systems face challenges in reducing write interference on adjacent memory cells and improving access performance, particularly in high-frequency write operations.
Innovation Solution
A memory system with a memory controller that refreshes adjacent memory cells of a target memory cell when the count of write operations within a preset time duration exceeds a preset threshold, using different time durations and thresholds to manage write interference effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If write operations are performed frequently on target memory cells to improve storage performance, then productivity is improved, but write interference on adjacent memory cells increases causing reliability deterioration
Solution Approach 1:
The patent performs preliminary refresh operations on adjacent memory cells before they are affected by write interference. The memory controller monitors write operations to target memory cells and proactively refreshes adjacent cells that are likely to be affected, preventing data loss before it occurs.
Solution Approach 2:
The patent implements a feedback mechanism where the memory controller counts write operations on target memory cells within a time window and uses this information to determine when to refresh adjacent memory cells. This feedback-driven approach dynamically adjusts refresh operations based on actual write activity patterns.
2Reliability
If refresh operations are performed on adjacent memory cells to reduce write interference, then reliability is improved, but access time increases
Solution Approach 1:
The patent performs refresh operations only on specific adjacent memory cells that are determined to be affected by write interference, rather than refreshing all memory cells. This partial action approach reduces the time overhead while maintaining reliability for the affected cells.
Solution Approach 2:
The patent implements periodic refresh operations based on time windows and write operation counts. Instead of continuous monitoring and refreshing, the system checks write operation counts at periodic intervals and performs refresh operations only when thresholds are exceeded, reducing overall access time overhead.
3Reliability
If multiple time durations and thresholds are used to manage write interference, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent uses multiple time durations and threshold values as adjustable parameters to optimize write interference management. Different time windows and thresholds can be configured based on specific workload patterns and memory characteristics, allowing the system to adapt to different scenarios without fundamental changes to the control architecture.
Data Source
AI summary
Systems, devices, methods, and storage media for managing refreshment of memory cells in memory systems are provided. In one aspect, a memory system includes: a non-volatile memory device including a plurality of memory cells and a memory controller coupled to the non-volatile memory device. The memory controller is configured to: refresh adjacent memory cells of a target memory cell of the plurality of memory cells, when a count of write operations performed on the target memory cell within a preset time duration is greater than a preset threshold.