Memory Controller Refresh Coordination to Reduce Stream Interruptions
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Solution Overview
Problem
Existing refresh methods for dynamic random access memory (DRAM) lead to high probabilities of stream interruptions in memory access due to independent channel refresh operations, affecting memory access efficiency.
Innovation Solution
A refresh processing method and system where multiple memory controllers communicate to determine a refresh policy for each memory space based on indication signals and refresh information, synchronizing refresh operations to reduce the likelihood of stream interruptions during continuous memory access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If multiple channels are independently refreshed, then each memory controller can autonomously manage its memory space, but the probability of stream interruption increases and memory access efficiency deteriorates
Solution Approach 1:
The patent merges the refresh control of multiple independent channels into a coordinated system. Memory controllers exchange indication signals about their refresh status and idle states, allowing them to synchronize refresh operations. This combination reduces the probability that all channels will be interrupted simultaneously, thereby improving memory access efficiency while maintaining autonomous management capabilities.
Solution Approach 2:
The patent implements feedback mechanisms where memory controllers send indication signals to each other about their refresh status and idle states. Based on this feedback information, controllers can dynamically adjust their refresh timing to avoid simultaneous interruptions. This feedback loop enables coordinated refresh operations that maintain operational autonomy while improving overall system productivity.
2Device complexity
If channels are refreshed independently, then device complexity is reduced, but stream interruption probability increases
Solution Approach 1:
The patent introduces indication signals as intermediaries between independent memory controllers. These signals carry information about refresh status and idle states, enabling controllers to coordinate their operations without requiring complex direct integration. This intermediary mechanism maintains relatively simple device architecture while significantly improving stream continuity by reducing simultaneous interruptions.
3Productivity
If refresh operations are synchronized across multiple channels, then memory access efficiency is improved, but device complexity increases
Solution Approach 1:
The patent segments the refresh coordination function into simple indication signals exchanged between controllers, rather than requiring a complex centralized control structure. Each controller maintains its independence while exchanging minimal status information (idle state and refresh status). This segmentation approach enables synchronized refresh operations that improve memory access efficiency without substantially increasing device complexity.
Data Source
AI summary
A refresh processing method, apparatus, and system, and memory controllers are provided, to improve memory access efficiency. The refresh processing apparatus includes a plurality of memory controllers that are in one-to-one correspondence with a plurality of memory spaces. Any first memory controller in the plurality of memory controllers is configured to: receive N first indication signals and N second indication signals that are output by N memory controllers other than the first memory controller, where N is greater than or equal to 1; and determine a refresh policy of a first memory space based on at least one of the following information: the N first indication signals, the N second indication signals, and refresh indication information of the first memory space.