Memory Controller Refresh Logic for Low-Retention DRAM Rows
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Solution Overview
Problem
As process geometries shrink in dynamic random access memories (DRAMs), cell retention times decrease, leading to discarded devices and increased refresh rates or reduced yield, as manufacturers struggle to maintain data retention over specified intervals.
Innovation Solution
Implementing address-differentiated refresh rates by distinguishing between normal-retention and low-retention storage rows, where low-retention rows are refreshed at a faster rate, using a memory controller to manage primary and secondary refresh rates and redirecting refresh operations to optimize cell retention without increasing the total number of refresh operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the refresh rate is increased to maintain data retention in low-retention storage rows, then cell retention reliability is improved, but refresh overhead increases and performance deteriorates
Solution Approach 1:
The patent applies different refresh rates to different storage rows based on their retention characteristics. Low-retention rows receive faster refresh rates while normal-retention rows use standard refresh rates, optimizing energy consumption by applying intensive refresh only where necessary rather than uniformly across all rows.
Solution Approach 2:
The patent segments the storage array into low-retention storage rows and normal-retention storage rows, allowing independent refresh rate management for each segment. This segmentation enables the system to address retention issues in specific rows without increasing the refresh overhead for the entire memory device.
2Reliability
If the refresh rate is increased to accommodate low-retention storage rows, then data retention is improved, but manufacturing yield decreases due to higher refresh overhead
Solution Approach 1:
The patent implements local quality differentiation by identifying and separately managing low-retention rows through address-differentiated refresh. This allows the memory device to meet retention requirements for problematic rows without forcing a global increase in refresh rate that would reduce overall device yield and performance.
3Productivity
If address-differentiated refresh rates are implemented to salvage low-retention rows, then production yield is improved, but device complexity increases due to additional refresh management logic
Solution Approach 1:
The memory device performs self-service by automatically identifying low-retention rows through initialization procedures and configuring the refresh rate map internally. This self-configuration approach reduces the need for external controller complexity while enabling yield improvement through differentiated refresh management.
Solution Approach 2:
The patent performs preliminary identification and classification of low-retention rows during device initialization before normal operation begins. The refresh rate map is pre-configured based on retention characteristics detected during initialization, allowing the device to operate with optimized refresh rates without adding complexity to the main operational logic.
4Reliability
If normal refresh operations are redirected to low-retention storage rows, then cell retention is improved, but the number of refresh operations for normal-retention rows decreases
Solution Approach 1:
The patent applies refresh operations with local quality differentiation, directing enhanced refresh attention to low-retention rows through a configurable rate map. This ensures that rows with retention problems receive the necessary refresh frequency while normal-retention rows are refreshed at standard rates, maintaining overall system efficiency.
Data Source
AI summary
A memory controller is disclosed that provides refresh control circuitry to generate first refresh commands directed to a first row of storage cells within a memory device at a first rate. The refresh control circuitry generates second refresh commands directed to a second row of storage cells within the memory device at a second rate. Output circuitry outputs the first and second refresh commands to the memory device.