Memory Controller Mapping for Non-Power-of-Two Memory Sizes
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Solution Overview
Problem
Existing memory access techniques struggle to efficiently utilize memory space when the number of memory controllers and the size of memory devices are not powers of two, leading to non-contiguous memory utilization and inefficiencies requiring software specialization.
Innovation Solution
A system and method that divides the memory space into N*k regions, where N is the number of memory controllers and devices, and k is a factor making the device size a multiple of a power of two, allowing even distribution and mapping of memory devices to these regions using a masking algorithm.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the memory space is divided into regions based on address bits for non-power-of-two memory controllers, then the memory space can be distributed among regions, but holes are introduced which are regions not mapped to physical memory
Solution Approach 1:
The memory space is segmented into multiple regions (first set and second set of regions) that are mapped to different memory devices. Each region is assigned to specific memory devices based on the mapping relationship, ensuring that all physical memory locations are utilized without creating unmapped holes in the memory space.
Solution Approach 2:
The patent introduces a new dimension to the mapping problem by creating multiple region sets that map to different memory devices. Instead of a single linear mapping that creates holes, the system uses multi-dimensional region mapping where each region set covers different portions of the memory space, ensuring complete coverage without gaps.
2Loss of substance
If a power of two size memory space is created larger than the physical memory to avoid holes, then holes are avoided, but non-contiguous memory space utilization results
Solution Approach 1:
The memory space is divided into multiple contiguous regions that map to different memory devices. By segmenting the address space into first and second sets of regions, each mapping to specific memory devices, the system achieves contiguous memory utilization without requiring a larger power-of-two memory space that would create gaps.
3Loss of substance
If software specialization is implemented to account for holes in memory space, then memory access can be managed, but system efficiency decreases
Solution Approach 1:
The memory mapping system is designed to automatically handle the mapping between memory addresses and physical memory locations without requiring software specialization. The mapping logic is embedded in the memory controller hardware, which automatically routes memory requests to the appropriate memory devices based on the region mapping, eliminating the need for software to account for memory holes.
4Adaptability or versatility
If the number of memory controllers is not a power of two, then flexible system configuration is achieved, but the hashing algorithm cannot be used for mapping
Solution Approach 1:
The mapping problem for non-power-of-two memory controllers is solved by segmenting the memory space into multiple region sets. Each region set is mapped to specific memory devices using simplified mapping logic, avoiding the need for complex hashing algorithms while supporting flexible memory controller configurations.
Solution Approach 2:
The patent changes the mapping approach from hashing-based to region-based mapping. By parameterizing the memory space into discrete regions that map to memory devices, the system achieves efficient mapping for non-power-of-two configurations without requiring hashing algorithms, thus reducing computational complexity.
Data Source
AI summary
A system including a memory space that is accessible for reading or writing data, a plurality of N memory devices including physical locations corresponding to the memory space, wherein a size of each memory device is not a power of two, and is a multiple of a power of two by a factor of k, wherein k is an integer, and one or more processors. The processors assign addresses of the memory space to a plurality of N*k regions and map each of the plurality of N memory devices to a subset of the plurality of N*k regions.