Memory Controller RAID Parity via Relative Addressing
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Solution Overview
Problem
Conventional data striping techniques require extensive processing time and storage resources due to the need for storage of logical to physical address mappings for every stripe unit, which limits the efficiency of data transfer across multiple memory devices.
Innovation Solution
A method where a single data transfer request with a contiguous instruction portion and multiple data segments is transmitted to multiple memory portions, allowing each to identify and store its corresponding segment, and optionally performing XOR operations or using seed values to optimize data storage and retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional data striping is used to spread data across multiple devices, then data throughput is increased, but processing time increases due to the need to store logical to physical address mappings for every stripe unit
Solution Approach 1:
The patent extracts and eliminates the address mapping overhead from conventional data striping by introducing relative memory addresses that are automatically calculated by each memory portion based on its identifier. This removes the need to store and process separate address mappings for each stripe unit, thereby reducing processing time while maintaining the parallel data distribution capability that increases throughput.
Solution Approach 2:
Each memory portion automatically determines its own data segment location using its unique identifier and the relative memory address from the single data transfer request. This self-service mechanism eliminates the need for centralized address mapping management, reducing the controller's processing burden and overall system processing time while preserving efficient parallel data writing.
2Reliability
If address mappings are stored for every stripe unit, then data can be accurately located across multiple devices, but storage resources are consumed
Solution Approach 1:
The patent removes the address mapping data structure from the system by implementing a calculation-based addressing scheme. Each memory portion computes its data segment address using its identifier and the relative address from the transfer request, eliminating the need to allocate storage resources for maintaining address mapping tables while ensuring accurate data location through deterministic address calculation.
Solution Approach 2:
The patent changes the addressing parameter from absolute physical addresses requiring storage to relative addresses that are automatically offset by each memory portion's identifier. This parameter transformation maintains precise data location capability while eliminating the storage overhead associated with maintaining address mapping information.
3Ease of operation
If multiple data transfer requests are sent to multiple memory portions, then each portion can identify its data segment, but processing time increases
Solution Approach 1:
The patent merges multiple separate data transfer requests into a single unified request that contains a relative memory address applicable to all memory portions. Each memory portion independently calculates its specific address by combining the relative address with its identifier, maintaining clear data segment identification while reducing the number of request processing operations and thereby decreasing processing time.
Data Source
AI summary
A memory controller receives a command to perform a memory operation, the command including a data packet comprising a plurality of data divisions. In response to receiving the command, for each individual memory device, the memory controller assigns to the individual memory device a respective data division, the respective data division including a plurality of data segments, and determines a single relative memory address associated with an address specified by the received command. The memory controller assembles a sub-request comprising a single contiguous instruction portion, which includes the single relative memory address and one or more instructions to perform the memory operation, and the respective data division, the respective data division following the single contiguous instruction portion, and transmits the sub-request to every memory portion of the number of memory portions of the individual memory device.