DRAM Memory Controller Reordering Logic Area Reduction

The request buffer is divided into multiple stages (first stage, second stage, third stage) with different functions. The first stage performs initial request intake and basic filtering, the second stage performs detailed reordering analysis, and the third stage handles command generation. This segmentation allows the complex reordering logic to be distributed across multiple simpler modules, reducing the area of any single logic circuit while maintaining overall reordering functionality.

Requests are pre-processed and categorized in earlier stages before reaching the main reordering logic. Bank and page state information is pre-fetched and prepared in advance, so when requests need reordering, the logic circuit already has the necessary contextual information available, reducing the complexity of real-time decision-making circuits.

Each stage of the request buffer is assigned a specific, limited function rather than requiring all stages to perform complete reordering analysis. The first stage handles basic request validation and initial sorting, the second stage performs intermediate reordering based on bank states, and the third stage completes the reordering and generates commands. This functional segmentation allows multiple stages to exist without exponentially increasing logic circuit area.

The patent introduces a temporal dimension to the reordering process by using multiple stages that process requests sequentially through time rather than requiring all reordering logic to operate simultaneously. This transforms a spatial complexity problem (all logic needed at once) into a temporal process (logic applied in sequence), reducing the peak logic circuit area required.