Memory Controller Repairing Defective Cells Without Extra Layout Area
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Solution Overview
Problem
High integration in semiconductor memory devices leads to increased failure probability during fabrication, and existing repair methods, such as fuse cutting and electrical fuse cutting, require additional layout area and do not allow for multiple programming operations, making it impossible to repair failures that occur during device use.
Innovation Solution
An integrated circuit with a memory controller that determines defective memory cells, extracts their addresses, and replaces them with redundant cells during a test mode, eliminating the need for multiple fuses and high voltage circuits, allowing for in-use repair without increasing layout area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fuse cutting method or electrical fuse cutting method is used to repair failed memory cells, then the failed memory cells can be replaced with normal memory cells, but the layout area of the semiconductor memory device increases due to additional fuses, electrical fuse circuits, and high voltage generation circuits
Solution Approach 1:
The patent extracts the repair functionality from external repair equipment (laser, high voltage generation circuits) and integrates it directly into the memory device by embedding repair data in the column address buffer. This eliminates the need for separate repair circuits and external repair equipment, thereby reducing layout area while maintaining repair capability
Solution Approach 2:
The column address buffer is designed to serve dual purposes: normal column address storage during operation and repair data storage during repair mode. This multi-functionality eliminates the need for dedicated repair circuits, reducing overall layout area while maintaining both operational and repair functionality
2Reliability
If fuse cutting method or electrical fuse cutting method is used, then memory cell repair is possible, but multiple programming operations cannot be performed and repairs during device use are impossible
Solution Approach 1:
The patent implements a dynamic repair system where the column address buffer can be reprogrammed multiple times. The repair mode is activated by specific control signals (REP1, REP2) that allow the buffer to switch between normal operation and repair modes, enabling flexible programming operations and post-manufacturing repairs during device use
Solution Approach 2:
The patent prepares repair data in advance by storing it in the column address buffer during manufacturing or before use. The repair addresses and corresponding redundant column addresses are pre-loaded into the buffer, allowing quick activation of repair mode without requiring external repair equipment during actual repair operations
Data Source
AI summary
An integrated circuit includes: a memory controller configured to determine whether a memory cell included in a semiconductor memory device is defective or not and extract a fail address having positional information of the defective memory cell, in a test mode; and a fail address storage unit configured to store the fail address.