Memory Controller Repair Using Shared Storage Spaces
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor memory systems, the increasing number of faulty addresses in large memory devices leads to a significant increase in the area required for content addressable memory (CAM) storage, resulting in a larger memory controller repair area, which is inefficient and costly.
Innovation Solution
A semiconductor memory device with a memory controller that includes a normal operation control part and a repair part, where the repair part uses shared storage spaces with a pipeline structure to store faulty addresses detected during testing, eliminating the need for extra storage space in the BIRA circuit and reducing the area overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a content addressable memory (CAM) is used to store faulty addresses in the BIRA circuit, then faulty addresses can be stored and analyzed, but the area occupied by the CAM increases significantly with the number of faulty addresses
Solution Approach 1:
The patent merges the storage function of the BIRA circuit with the normal operation control part by utilizing the existing plurality of storage spaces (212-1, 212-2, 212-3) that are already present in the memory controller. Instead of adding a separate CAM structure, the faulty addresses are stored in the same storage spaces used for normal operations, thereby eliminating the need for additional CAM area while maintaining the capability to store and analyze faulty addresses
Solution Approach 2:
The storage spaces in the normal operation control part are designed to serve multiple functions: they store data during normal memory operations and also store faulty addresses during repair operations. This multi-functionality allows the same hardware resources to be reused for different purposes, reducing the overall area requirement without compromising either normal operation or repair functionality
2Reliability
If separate high-cost test apparatuses are used to test and repair embedded memory devices, then fabrication yield and quality improve, but total fabrication cost increases
Solution Approach 1:
The memory controller is equipped with a built-in self-test (BIST) circuit and built-in redundancy analysis (BIRA) circuit that enable the memory device to test and repair itself without requiring external test apparatuses. This self-service capability allows the device to detect faulty addresses through BIST and perform repair operations through BIRA using the same storage spaces, thereby eliminating the need for separate high-cost test equipment while maintaining fabrication quality
3Reliability
If the number of spare cells is increased to handle more faulty addresses, then repair capability improves, but the memory device area increases
Solution Approach 1:
The patent combines the storage resources for normal operations and repair operations into a single shared storage structure. The plurality of storage spaces are used both for normal data operations and for storing faulty addresses during repair operations, eliminating the need for separate spare storage areas and reducing overall memory device area while maintaining full repair capability
Data Source
AI summary
A semiconductor memory device includes a memory and a memory controller configured to control the memory. The memory controller includes a normal operation control part and a repair part. The normal operation control part is configured to control a normal operation of the memory and includes a plurality of storage spaces used while the normal operation is controlled. The repair part is configured to control a repair operation of the memory and stores faulty addresses detected while the repair operation is controlled into the plurality of storage spaces included in the normal operation control part.