Memory Controller Replay Circuit for Non-Volatile Read Grouping
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Solution Overview
Problem
The integration of non-volatile memory with volatile memory in computer systems poses challenges due to the slower and nondeterministic nature of non-volatile reads, which complicates the design of memory controllers that can effectively manage and recover from errors in heterogeneous memory environments.
Innovation Solution
A memory controller architecture that includes a command queue, memory interface queue, storage queue, and replay control circuit, which detects errors and initiates a recovery sequence by grouping non-volatile read commands separately from volatile and non-volatile write commands, allowing for efficient error handling and recovery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If non-volatile memory reads are handled in the same queue as volatile memory reads, then queue management is simpler, but error recovery becomes more complex and time-consuming due to nondeterministic read completion times
Solution Approach 1:
The patent divides the memory access queue into separate segments: a first queue for volatile memory access commands and a second queue for non-volatile memory access commands. This segmentation allows independent handling of each memory type, enabling deterministic error recovery for volatile memory while accommodating the nondeterministic nature of non-volatile memory reads without complicating the overall queue management structure.
Solution Approach 2:
The patent introduces a queue management circuit as an intermediary between the host interface and the memory interface. This circuit automatically selects which queue to service based on the memory type, transparently managing the complexity of error recovery procedures while maintaining simple queue structures for each memory type.
2Reliability
If non-volatile read commands are grouped separately from volatile and non-volatile write commands, then error recovery is improved, but queue length increases due to nondeterministic latencies
Solution Approach 1:
The patent segments non-volatile read commands into a separate second queue, isolated from volatile and non-volatile write commands. This segmentation enables independent error recovery procedures for reads without affecting write operations, improving reliability while managing queue lengths through type-specific handling.
Solution Approach 2:
The patent changes the operational parameters of the queues by implementing type-specific service policies. The queue management circuit adjusts service timing and error recovery parameters based on whether the command is volatile or non-volatile, allowing optimized queue length management for each command type rather than using a single conservative parameter set.
3Device complexity
If a single queue is used for all memory access commands, then device complexity is reduced, but productivity decreases due to inability to optimize handling for different memory types
Solution Approach 1:
The patent implements a segmented queue architecture with a first queue for volatile memory commands and a second queue for non-volatile memory commands. This segmentation enables the controller to optimize handling for each memory type independently, improving productivity through type-specific optimization while maintaining relatively simple queue structures that do not significantly increase device complexity.
Solution Approach 2:
The patent introduces dynamic queue management where the queue management circuit adaptively selects which queue to service based on current memory access patterns and command types. This dynamic approach allows the controller to optimize productivity for different workloads while maintaining a fixed, manageable queue architecture.
Data Source
AI summary
A memory controller includes a command queue, a memory interface queue, at least one storage queue, and a replay control circuit. The command queue has a first input for receiving memory access commands. The memory interface queue receives commands selected from the command queue and couples to a heterogeneous memory channel which is coupled to at least one non-volatile storage class memory (SCM) module. The at least one storage queue stores memory access commands that are placed in the memory interface queue. The replay control circuit detects that an error has occurred requiring a recovery sequence, and in response to the error, initiates the recovery sequence. In the recovery sequence, the replay control circuit transmits selected memory access commands from the at least one storage queue by grouping non-volatile read commands together separately from all pending volatile reads, volatile writes, and non-volatile writes.