Memory Controller Replication for NVRAM Latency

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Solution Overview

Problem

Non-volatile random access memories (NVRAM) exhibit higher memory access latencies, particularly for write requests, which can lead to performance degradation and user experience issues in real-time applications like video playback, due to high-latency write operations causing memory access contention.

Innovation Solution

The method involves replicating write data across multiple memory banks to alleviate contention, allowing read requests to be serviced from available banks while the primary bank is busy with writes, using a memory controller to determine contention conditions and issue replicated write commands to other banks, thereby reducing average read latencies.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If write requests are processed in non-volatile memory banks, then data persistence is achieved, but memory access latency increases significantly

Engineering Contradiction:
Improvedata persistenceVSAvoidmemory access latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The memory system is divided into multiple independent memory banks, each capable of handling write requests simultaneously. This segmentation allows the system to distribute write operations across multiple banks, reducing the latency impact on any single bank while maintaining data persistence in non-volatile memory.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements a copying mechanism where data is replicated across multiple memory banks. When a write request targets a busy bank, the system can copy the data to an available bank, allowing read requests to be serviced from the copied data while the original bank completes its write operation. This maintains data persistence while reducing access latency.

Inventive Principle:
Principle #26Copying

2Reliability

If write operations are performed in a memory bank, then data is stored persistently, but read requests to the same bank are blocked

Engineering Contradiction:
Improvedata storageVSAvoidmemory access throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

By segmenting the memory system into multiple independent banks, the patent enables parallel processing of read and write requests across different banks. When one bank is performing a persistent write operation, other banks remain available to service read requests, thereby maintaining high memory access throughput while ensuring data storage reliability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a memory controller that acts as an intermediary, managing data replication across multiple banks. When a write request is issued, the controller can replicate data to multiple banks, allowing read requests to be serviced from replicated data in available banks while the original write completes in the target bank, thus preventing read blocking.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Ease of operation

If write pausing is implemented to allow reads in the same bank, then read access is enabled, but overall memory operation speed decreases

Engineering Contradiction:
Improveread access availabilityVSAvoidmemory operation speed
Core Design Contradiction:
Ease of operationVSSpeed

Solution Approach 1:

The memory system is segmented into multiple independent banks, eliminating the need for write pausing within the same bank. When a write operation is in progress in one bank, read requests can be directed to other available banks or to replicated copies of the data, allowing continuous memory operations without pausing and maintaining high operation speed while ensuring read access availability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements preliminary data replication before write operations complete. By copying data to multiple banks in advance, the system ensures that read requests can be serviced immediately from replicated data without waiting for write operations to complete, thereby maintaining both read access availability and high memory operation speed without requiring write pausing.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10515671B2Method and apparatus for reducing memory access latency
Publication Date: 2019.12.24 ADVANCED MICRO DEVICES INC
  • US10515671B2 patent drawing
  • US10515671B2 patent drawing
  • US10515671B2 patent drawing

AI summary

Logic such as a memory controller writes primary data from an incoming write request as well as corresponding replicated primary data (which is a copy of the primary data) to one or more different memory banks of random access memory in response to determining a memory access contention condition for the address (including a range of addresses) corresponding to the incoming write request. When the memory bank containing the primary data is busy servicing a write request, such as to another row of memory in the bank, a read request for the primary data is serviced by reading the replicated primary data from the different memory bank of the random access memory to service the incoming read request.