Memory Controller Hardware Fallback for Traffic-Aware Reset Timing
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Solution Overview
Problem
Existing memory systems with volatile memory devices like DRAM face performance issues when firmware malfunctions, leading to sudden termination and system crashes due to immediate resets, which can disrupt data dumping and affect overall system performance.
Innovation Solution
A memory system and method that utilizes hardware to communicate with a host and monitor access traffic, allowing for controlled resets of the memory device only when traffic is below a threshold, thereby minimizing performance disruptions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If immediate reset is performed when firmware malfunction is detected, then system reliability is improved, but system performance deteriorates due to disruption of data dumping and operations
Solution Approach 1:
The reset decision is made dynamic based on real-time monitoring of access traffic. The memory controller continuously monitors the access traffic count and compares it against a threshold value, adjusting the reset decision accordingly. When access traffic exceeds the threshold, reset is delayed to maintain performance; when traffic falls below the threshold, reset is executed to ensure reliability.
Solution Approach 2:
The system implements a feedback mechanism where the memory controller monitors access traffic in real-time and uses this information to determine whether to perform a reset. The monitoring of access traffic count provides continuous feedback that influences the reset decision, allowing the system to balance between reliability and performance based on actual operational conditions.
2Productivity
If reset is delayed to maintain data communication, then system performance is improved, but reliability deteriorates due to potential firmware malfunction continuation
Solution Approach 1:
The reset timing is dynamically adjusted based on real-time access traffic conditions. The system does not use a fixed reset policy but rather adapts the reset timing based on whether access traffic is above or below the threshold, allowing delayed reset when performance is critical and immediate reset when reliability is prioritized.
Solution Approach 2:
The system changes the parameter of reset timing based on the access traffic count threshold. By using the access traffic count as a decision parameter, the system can shift between different operational modes: performance-mode (delayed reset) when traffic is high and reliability-mode (immediate reset) when traffic is low, thus resolving the contradiction between performance and reliability.
3Ease of operation
If access traffic monitoring is implemented, then controlled reset capability is improved, but device complexity increases
Solution Approach 1:
The memory controller leverages its existing multi-functional capabilities to perform access traffic monitoring and threshold comparison, in addition to its primary function of controlling memory operations. By utilizing the existing controller's processing resources and control logic, the system achieves controlled reset capability without adding separate dedicated monitoring hardware, thus minimizing the increase in device complexity.
Data Source
AI summary
A memory system may include a memory device and a memory controller. The memory controller may execute firmware which controls the memory device, perform, when an abnormal event of the firmware is sensed, data communication with a host, based on hardware in place of the firmware, and reset the memory device when the access traffic is a threshold value or less.