Memory Controller Dynamic Read Voltage Adjustment

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Solution Overview

Problem

Current memory controllers do not effectively optimize read voltage settings based on the retention period and program/erase count of memory devices, leading to inefficiencies in data storage and retrieval operations.

Innovation Solution

A memory controller that determines a remaining count of program and erase operations, calculates a retention period based on power-off and power-on times, and adjusts read voltages using a changed read voltage table generated from a default table and a coefficient, to optimize read operations in memory devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If read voltage settings are fixed based on default tables, then device complexity is reduced, but read operation accuracy and reliability deteriorate due to inability to adapt to retention period and program/erase count variations

Engineering Contradiction:
Improveread operation accuracyVSAvoidvoltage adjustment mechanism
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements dynamic read voltage adjustment by transitioning from fixed default voltage tables to adaptive voltage selection based on retention period and program/erase count. The memory controller dynamically determines appropriate read voltages by calculating retention periods from power-off/power-on times and adjusting voltages according to remaining program/erase counts, thereby maintaining read operation accuracy across varying operational conditions without requiring complex hardware modifications

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the parameters used for voltage determination from static default tables to dynamic parameters including retention period (calculated from power-off and power-on times) and program/erase count (determined from remaining operation counts). By modifying these parameters and their relationship to read voltage selection, the system achieves adaptive voltage adjustment that improves read accuracy while managing complexity through algorithmic rather than hardware-based solutions

Inventive Principle:
Principle #35Parameter changes

2Productivity

If read voltages are adjusted dynamically based on retention period and program/erase count, then read operation efficiency and lifespan are improved, but device complexity increases

Engineering Contradiction:
Improveread operation efficiencyVSAvoidcontrol logic
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The memory controller performs self-service by autonomously calculating retention periods from its own power-off and power-on time records and determining appropriate read voltages based on its internal program/erase count tracking. This self-determination mechanism enables dynamic voltage adjustment and improved read efficiency without requiring external intervention or additional complex control systems, as the controller uses its own operational data to optimize its performance

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent implements feedback mechanisms where the memory controller continuously monitors retention period (derived from power cycle times) and program/erase count status, then uses this feedback information to adjust read voltages accordingly. This closed-loop approach allows the system to adapt to changing operational conditions and wear states, improving read efficiency and extending device lifespan through data-driven voltage optimization

Inventive Principle:
Principle #23Feedback

3Speed

If default read voltage tables are used without modification, then ease of operation is maintained, but operational speed and efficiency deteriorate due to lack of optimization

Engineering Contradiction:
Improveoperational speedVSAvoidvoltage configuration
Core Design Contradiction:
SpeedVSEase of operation

Solution Approach 1:

The patent applies preliminary action by pre-calculating and storing multiple read voltage tables corresponding to different retention periods and program/erase count ranges. When read operations are required, the controller selects from these pre-prepared voltage tables based on current operational conditions, thereby achieving optimized operational speed without requiring complex real-time voltage calculation or configuration during operation

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11238926B2Memory controller and operating method thereof
Publication Date: 2022.02.01 SK HYNIX INC
  • US11238926B2 patent drawing
  • US11238926B2 patent drawing
  • US11238926B2 patent drawing

AI summary

A memory controller having an improved operation speed controls a memory device including a plurality of memory blocks. The memory controller includes: a remaining count determiner configured to determine a remaining count that is a number of program and erase operations to be additionally performed in the memory device based on a program/erase count received from the memory device, a retention period calculator configured to determine a retention period based on a power-off time and a power-on time of the memory device and a read voltage determiner configured to generate a changed read voltage table based on a default read voltage table and a coefficient determined according to the remaining count, and determine a read voltage to be used in the memory device according to the retention period among read voltages included in the changed read voltage table.