Memory Controller Retry Pipeline for CAPE Error Handling
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Solution Overview
Problem
The existing memory controller systems face inefficiencies in request processing due to the need for a retry window, which increases circuit scale and complexity, particularly when handling command address bus parity errors (CAPEs), leading to reduced performance and increased material costs.
Innovation Solution
A memory controller with a request pipeline and a retry control unit that stops new requests when an error occurs, allowing subsequent requests to be retried using stored information in the pipeline, thereby reducing the need for additional circuitry and improving out-of-order processing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a retry window is implemented to handle CAPE errors, then request processing reliability is improved, but circuit scale and complexity increase
Solution Approach 1:
The patent merges the retry function with the existing request pipeline by reusing its storage resources. Instead of implementing a separate retry window circuit, the system combines retry functionality with the request pipeline's existing buffers, thereby improving reliability while avoiding additional circuit complexity.
Solution Approach 2:
The request pipeline is designed to serve multiple functions: normal request processing and error retry operations. By making the request pipeline universal, the system eliminates the need for dedicated retry circuitry, thus improving reliability without increasing device complexity.
2Reliability
If a retry window is implemented to handle CAPE errors, then request processing reliability is improved, but material costs increase
Solution Approach 1:
The patent merges the retry function with the existing request pipeline by reusing its storage resources. Instead of implementing a separate retry window circuit, the system combines retry functionality with the request pipeline's existing buffers, thereby improving reliability while avoiding additional circuit complexity.
3Reliability
If requests are retained in resources during the retry window period, then CAPE retry capability is improved, but request processing productivity decreases
Solution Approach 1:
The system dynamically manages request pipeline resources based on error conditions. During normal operation, the pipeline processes requests continuously with high productivity. When a CAPE error occurs, the system dynamically activates retry logic that reuses the same pipeline resources, maintaining productivity while enabling retry capability.
Solution Approach 2:
When a CAPE error occurs, the system discards the erroneous command and recovers by reissuing it through the existing request pipeline. This approach maintains productivity by quickly recovering from errors without permanently retaining requests, thus balancing retry capability with processing efficiency.
Data Source
AI summary
A memory controller includes a request pipeline and a retry control circuit. The request pipeline receives an input of a request to a memory output from a processor core, stores the request, and causes the memory to process the request in order of storage. The retry control circuit stops a new request input to the request pipeline when an error occurs in the memory, and re-inputs, to the request pipeline, requests to be retried that includes the request in which the error has occurred and a subsequent request stored in the request pipeline.